Patents Assigned to Elpida Memory
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Patent number: 8575763Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: September 9, 2010Date of Patent: November 5, 2013Assignee: Elpida Memory, Inc.Inventors: Masanori Yoshida, Fumitomo Watanabe
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Patent number: 8574998Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.Type: GrantFiled: December 5, 2011Date of Patent: November 5, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra Malhotra, Kenichi Koyanagi, Hiroyuki Ode, Xiangxin Rui, Takashi Arao, Naonori Fujiwara
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Patent number: 8576656Abstract: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.Type: GrantFiled: September 3, 2010Date of Patent: November 5, 2013Assignee: Elpida Memory, Inc.Inventor: Hiroki Fujisawa
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Patent number: 8576610Abstract: A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source and drain which is brought into an electrically floating state. The gate is connected to the signal line, and at least one of the source and drain is connected to a control node that is supplied with a control signal. The control signal is configured to receive a control signal that changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.Type: GrantFiled: July 15, 2011Date of Patent: November 5, 2013Assignee: Elpida Memory, Inc.Inventor: Soichiro Yoshida
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Patent number: 8574985Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.Type: GrantFiled: March 3, 2011Date of Patent: November 5, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Sunil Shanker, Sandra Malhotra, Imran Hashim, Edward Haywood
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Patent number: 8576652Abstract: A semiconductor memory device has an operation mode in which a read/write operation is performed in response to a command supplied externally in synchronization with a clock, and a power-down mode in which no external read/write command is accepted. The semiconductor memory device performs a refresh operation in response to an externally supplied signal during the power-down mode. A memory system has a plurality of the semiconductor devices and a memory controller. The memory controller outputs a control signal during the power-down mode, and the plurality of semiconductor devices perform a refresh operation in response to the control signal during the power-down mode.Type: GrantFiled: January 13, 2010Date of Patent: November 5, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
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Patent number: 8576639Abstract: A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit outputs and enables storage of a second logical value when the voltage provided from the terminal exceeds the threshold value. The output and storage occurs in the absence of an electrical connection between the cell and circuit. The switch provides voltage supplied from the terminal to the bit line of the circuit. The voltage increases from a value which does not exceed the threshold to a value which exceeds the threshold.Type: GrantFiled: July 5, 2011Date of Patent: November 5, 2013Assignee: Elpida Memory, Inc.Inventor: Giulio Martinozzi
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Patent number: 8574999Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.Type: GrantFiled: January 10, 2013Date of Patent: November 5, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
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Publication number: 20130286715Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).Type: ApplicationFiled: April 23, 2013Publication date: October 31, 2013Applicant: Elpida Memory, Inc.Inventor: Noriaki IKEDA
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Patent number: 8570815Abstract: When overdriving a first power supply voltage supplied to a sense amplifier, a line for the first power supply voltage and a line for a second power supply voltage which is higher than the first power supply voltage are connected to each other by a first transistor, thereby boosting the first power supply voltage. When the first power supply voltage drops upon activation of the sense amplifier, the line for the first power supply voltage and the line for the second power supply voltage are connected to each other by a second transistor, thereby increasing the current supply capability. The first transistor and the second transistor are fully driven to operate as switches.Type: GrantFiled: October 28, 2010Date of Patent: October 29, 2013Assignee: Elpida Memory, Inc.Inventor: Yuji Nakaoka
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Patent number: 8569819Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ??cm. Advantageously, the electrode layers are conductive molybdenum oxide.Type: GrantFiled: June 11, 2013Date of Patent: October 29, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Hiroyuki Ode
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Patent number: 8569898Abstract: Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.Type: GrantFiled: May 7, 2010Date of Patent: October 29, 2013Assignee: Elpida Memory, Inc.Inventors: Hiromasa Takeda, Satoshi Isa, Mitsuaki Katagiri, Dai Sasaki
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Patent number: 8569830Abstract: In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode which controls potential of a gate electrode material is formed in gate electrode material formed on a side surface of isolation film, in order to eliminate a parasitic MOS operation by the gate electrode material remaining on the side surface of the isolation film.Type: GrantFiled: September 2, 2008Date of Patent: October 29, 2013Assignee: Elpida Memory, Inc.Inventors: Kiyonori Oyu, Yoshihiro Takaishi, Yu Kosuge
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Patent number: 8569835Abstract: A semiconductor device includes a first pad, and a sub-trunk line elongated in a first direction; a main-trunk line arranged between the first pad and the sub-trunk line and elongated in the first direction. The semiconductor device further includes a first plug line elongated in a second direction crossing the first direction, the first plug line being connected between the first pad and the main-trunk line without being direct contact with the sub-trunk line. The semiconductor device further includes a second plug line elongated in the second direction, the second plug line being connected between the main-trunk line and the sub-trunk line, and a first element coupled to the sub-trunk line.Type: GrantFiled: October 27, 2010Date of Patent: October 29, 2013Assignee: Elpida Memory, Inc.Inventors: Koji Yasumori, Hisayuki Nagamine
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Publication number: 20130283001Abstract: Disclosed herein is a device that includes: a data terminal; a plurality of memory banks; and a control circuit configured to control a data transfer between the data terminal and the memory banks. The control circuit is configured to set a read latency in response to a burst length.Type: ApplicationFiled: March 16, 2013Publication date: October 24, 2013Applicant: Elpida Memory, Inc.Inventor: Toru Ishikawa
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Patent number: 8564037Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.Type: GrantFiled: January 24, 2011Date of Patent: October 22, 2013Assignee: Elpida Memory, Inc.Inventor: Takeshi Kishida
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Patent number: 8565036Abstract: A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines, a word line driver which drives the word lines, and a plurality of word line potential stabilization transistors connected to the respective word lines and disposed on an opposite side of the word line driver with the memory cell array sandwiched between the word line potential stabilization transistors and the word line driver, each word line potential stabilization transistor turning on when the word line adjacent to a relevant one of the word lines is selected, thereby connecting the relevant word line to a non-selected potential, and turning off when the relevant word line is selected.Type: GrantFiled: May 11, 2011Date of Patent: October 22, 2013Assignee: Elpida Memory, Inc.Inventor: Makoto Kitayama
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Patent number: 8564361Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.Type: GrantFiled: March 13, 2013Date of Patent: October 22, 2013Assignee: Elpida Memory, Inc.Inventors: Hitoshi Tanaka, Kazutaka Miyano
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Patent number: 8565032Abstract: A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling edges of the third internal clock signal, an adjustment information holder supplying an edge adjustment signal to the edge adjustor, and a data strobe generator receiving the second and third internal clock signals to generate a first data strobe signal based on the second internal clock signal, and a second data strobe signal with a phase different from that of the first data strobe signal, based on the third internal clock signal. The edge adjustor adjusts the timing of at least one of the rising and falling edges of the third internal clock signal based on the edge adjustment signal.Type: GrantFiled: April 4, 2011Date of Patent: October 22, 2013Assignee: Elpida Memory, Inc.Inventor: Tsuneo Abe
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Patent number: 8563392Abstract: In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.Type: GrantFiled: December 5, 2011Date of Patent: October 22, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra Malhotra, Wim Deweerd, Edward Haywood, Hiroyuki Ode