Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width.

Abstract: A semiconductor device includes a semiconductor substrate having a groove; a gate insulator; a first diffusion region; a gate electrode; a hydrogen-containing insulator; and a fluorine-containing insulator. The gate insulator covers inside surfaces of the groove. The first diffusion region is formed in the substrate. The first diffusion region has a first contact surface that contacts the gate insulator. The gate electrode is formed on the gate insulator and in the groove. The hydrogen-containing insulator is formed over the gate electrode and in the groove. The hydrogen-containing insulator is adjacent to the gate insulator. The fluorine-containing insulator is formed on the hydrogen-containing insulator and in the groove. The first contact surface includes Si—H bonds and Si—F bonds.

Abstract: An exposure method includes the following processes. An autofocus scan process is performed to detect a defocused portion of a first resist film over a semiconductor wafer and to generate a detection signal that indicates the defocused portion detected. A first exposure scan process is performed while selectively blinding the first resist film, with reference to a detection signal related to the defocused portion detected.

Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.

Abstract: A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.

Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.

Abstract: For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.

Abstract: Disclosed herein is a device that includes: a first timing adjustment circuit generating a first control signal based on a command and an output buffer outputting a plurality of data sets in a serial at a timing based on the first control signal; and a second semiconductor chip including: a plurality of holding circuits holding the data sets in parallel, a second timing adjustment circuit generating a second control signal based on the command, and an input buffer sequentially capturing the data sets supplied from the holding circuits based on the second control signal.

Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.

Abstract: Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.

Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.

Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: Semiconductor apparatus includes first power supply line and second power supply line, first sub power supply line, first switch circuit, first logic circuit and first control circuit. First switch circuit is disposed between first power supply line and first sub power supply line, and controlled based on first signal. First logic circuit is disposed between first sub power supply line and second power supply line and comprises first input node and second input node receiving second signal and third signal respectively, and output node. First logic circuit outputs an active voltage associated with a logical level of second signal to output node in active state, and outputs a standby voltage associated with a voltage of second power supply line to output node regardless of the logical level of second signal in non-active state.

Abstract: A semiconductor device includes a plurality of memory cells connected to a word line, sense amplifiers arranged correspondingly to the memory cells, and a sense-amplifier control circuit that activates the sense amplifiers in response to selection of the word line and temporarily reduces driving performance of the sense amplifiers in response to a request for writing of data to any one of the memory cells. With this configuration, inverted data can be quickly overwritten to the sense amplifier. Furthermore, because a collective control is executed on the sense amplifiers to be activated, instead of individually controlling the sense amplifiers to be activated, the circuit scale of the sense-amplifier control circuit can be reduced.

Abstract: To provide a semiconductor device including a temperature detection circuit that detects a temperature of the semiconductor device and outputs temperature information, a counter circuit that takes a count of repeated inputs of a refresh command and outputs count information, a comparison circuit that activates a match signal when the temperature information matches the count information, and a refresh control circuit that controls whether to perform a refresh operation according to activation of the refresh command based on the match signal. According to the present invention, a refresh cycle can be finely adjusted because the repeated inputs of the refresh command are thinned out based on the temperature information. With this configuration, power consumption caused by the refresh operation can be reduced.

Abstract: Disclosed herein is a device that includes a semiconductor substrate, a check circuit and a through-substrate via. The check circuit includes a check line formed over the semiconductor substrate and including first and second parts each extending in a first direction and a third part extending in a second direction that crosses the first direction, the first and second parts being opposite to each other, the third part connecting one end of the first part with one end of the second part, a charge circuit coupled to a one end of the check line, and a comparator coupled to the other end of the check line at a first input node thereof. The through-substrate via penetrates through the semiconductor substrate and is located in an area that is between the first and second parts of the check line.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.