Patents Assigned to ELPIS TECHNOLOGIES INC.
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Patent number: 11322359Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.Type: GrantFiled: May 14, 2020Date of Patent: May 3, 2022Assignee: ELPIS TECHNOLOGIES INC.Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
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Patent number: 11297717Abstract: An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.Type: GrantFiled: October 27, 2017Date of Patent: April 5, 2022Assignee: ELPIS TECHNOLOGIES INC.Inventor: Lei Shan
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Patent number: 11227796Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.Type: GrantFiled: September 18, 2019Date of Patent: January 18, 2022Assignee: ELPIS TECHNOLOGIES INC.Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson
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Patent number: 11177285Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.Type: GrantFiled: October 23, 2019Date of Patent: November 16, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Kangguo Cheng, Rama Divakaruni
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Patent number: 11088026Abstract: A device having co-integrated wimpy and nominal transistors includes first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region. The device also has wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region.Type: GrantFiled: December 17, 2019Date of Patent: August 10, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
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Patent number: 11063129Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.Type: GrantFiled: July 25, 2019Date of Patent: July 13, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
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Patent number: 10985257Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.Type: GrantFiled: March 22, 2019Date of Patent: April 20, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Choonghyun Lee, Brent A. Anderson, Injo Ok, Soon-Cheon Seo
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Patent number: 10978576Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.Type: GrantFiled: October 9, 2019Date of Patent: April 13, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Chi-Chun Liu, Chun Wing Yeung, Robin Hsin Kuo Chao, Zhenxing Bi, Kristin Schmidt, Yann Mignot
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Patent number: 10978454Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.Type: GrantFiled: January 30, 2020Date of Patent: April 13, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Brent Alan Anderson, Shawn P. Fetterolf, Terence B. Hook
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Patent number: 10966351Abstract: The present invention provides a heat dissipation device including a baseplate, one or more heat pipes in thermal communication with the baseplate, where the one or more heat pipes has one or more internal cavities, one or more vapor chambers coupled to the one or more heat pipes, where the one or more vapor chambers has one or more internal cavities, where the one or more internal cavities of the one or more heat pipes and the one or more internal cavities of the one or more the vapor chambers are contiguous, where the one or more vapor chambers extends from the one or more heat pipes, and heat conducting fins coupled to the one or more vapor chambers, where the one or more heat conducting fins extends from the one or more vapor chambers.Type: GrantFiled: November 13, 2019Date of Patent: March 30, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Xiaojin Wei, Allan C. VanDeventer
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Patent number: 10957536Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.Type: GrantFiled: November 1, 2019Date of Patent: March 23, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
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Patent number: 10943786Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.Type: GrantFiled: August 22, 2019Date of Patent: March 9, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Qing Cao, Shu-Jen Han, Ning Li, Jianshi Tang
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Patent number: 10937883Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.Type: GrantFiled: October 24, 2019Date of Patent: March 2, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
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Patent number: 10916468Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect.Type: GrantFiled: February 27, 2017Date of Patent: February 9, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Effendi Leobandung, Tenko Yamashita
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Patent number: 10886403Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.Type: GrantFiled: August 28, 2019Date of Patent: January 5, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Alexander Reznicek, Shogo Mochizuki, Jingyun Zhang, Xin Miao
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Patent number: 10833156Abstract: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.Type: GrantFiled: November 5, 2019Date of Patent: November 10, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Kevin K. Chan, Masaharu Kobayashi, Effendi Leobandung
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Patent number: 10832955Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.Type: GrantFiled: April 23, 2019Date of Patent: November 10, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Peng Xu, Kangguo Cheng, Yann Mignot, Choonghyun Lee
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Patent number: 10811410Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.Type: GrantFiled: June 3, 2019Date of Patent: October 20, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
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Patent number: 10804366Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.Type: GrantFiled: June 18, 2019Date of Patent: October 13, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
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Patent number: 10804107Abstract: A method for doping fins includes, for a first dopant layer formed in a first region and a second region to a height continuously below a top portion of a plurality of fins such that an entirety of the first dopant layer is formed below the top portion of the plurality of fins, and a dielectric layer formed over the top portion of the plurality of fins, removing the dielectric layer and the first dopant layer in the first region to expose a first fin in the first region, forming a second dopant layer over the first fin, and annealing to drive dopants into the fins from the first dopant layer in the second region and from the second dopant layer in the first region.Type: GrantFiled: November 1, 2019Date of Patent: October 13, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Effendi Leobandung, Tenko Yamashita