Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.

Abstract: A method for doping fins includes, for a first dopant layer formed in a first region and a second region to a height continuously below a top portion of a plurality of fins such that an entirety of the first dopant layer is formed below the top portion of the plurality of fins, and a dielectric layer formed over the top portion of the plurality of fins, removing the dielectric layer and the first dopant layer in the first region to expose a first fin in the first region, forming a second dopant layer over the first fin, and annealing to drive dopants into the fins from the first dopant layer in the second region and from the second dopant layer in the first region.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. A trench that extends through the device layer and partially through the buried insulator layer is formed. An electrically-conducting connection is formed in the trench.

Abstract: A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a wafer container having a bottom surface and a plurality of straps attached thereto placed within the shipping container. The package assembly further includes upper and lower force distribution plates provided within the shipping container positioned respectively on a top side and bottom side thereof.

Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: A wafer bonding method includes placing a first wafer on a first bonding framework including a plurality of outlet holes around a periphery of the first bonding framework. A second wafer is placed on a second bonding framework that includes a plurality of inlet holes around a periphery of the second bonding framework. The first bonding framework is in overlapping relation to the second bonding framework such that a gap exist between the first wafer and the second wafer. A gas stream is circulated through the gap between the first wafer and the second wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the first wafer and the second wafer.

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.

Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

Abstract: A self-assembled heteroepitaxial oxide nanocomposite film including alternating layers of a first metal oxide having a first melting point and a second metal oxide having a second melting point that differs from the first melting point is formed in an opening formed in a semiconductor substrate. After forming a metal or metal alloy via structure in the semiconductor substrate, first and second thermal treatments are performed to remove each layer of first or second metal oxide providing a nanoporous membrane.

Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.

Abstract: Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.

Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.

Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×104 nm2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.