Abstract: An optical tracking device and a method of operation thereof, including emitting light towards a surface at a first frequency with a first duration; receiving light reflected from the surface by an image sensor; determining image arrays from the received light, the image arrays including a first plurality of pixels; generating a first comparison array between the first image arrays generated at subsequent first intervals; and determining a first displacement amount based on the first comparison array. If the first displacement amount is bigger than a displacement amount threshold, emitting light towards the surface at second intervals of a second frequency, determining second image arrays from the received light, generating a second comparison array between the second image arrays generated at subsequent second intervals, and determining a second displacement amount based on the second comparison array.

Abstract: A method for obtaining reliable startup of a bandgap reference circuit, the bandgap reference circuit including a bandgap core with at least two branches, a feedback loop, and a startup circuit. The method includes generating a startup stimulus with an initial magnitude sufficient to transition the circuit from an inactive state to an active state, controlling the decline of the startup stimulus by regulating its reduction progressively over time, and modifying local time constants of the bandgap reference circuit to prevent a condition in which the transient decline of a voltage across a first branch is faster than the transient decline of a voltage across a second branch. By doing so, the voltages across the branches of the bandgap core converge to a target operating point, ensuring a reliable startup of the bandgap reference circuit.

Abstract: A semiconductor wafer (1a, 1b) including a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).

Abstract: A system and a method for generating a compensated received signal strength indicator (RSSI) value that corresponds to a radio frequency (RF) signal and a calibration method for such a system, including temperature compensation data for the amplification of RF induced voltages.

Abstract: Circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

Abstract: A rectifier circuit (10) for a passive RFID circuit (1). The rectifier circuit includes a first rectifier stage (11) including a first stage input (14) connectable to a first antenna port (6) and a second stage input (15) connectable to a second antenna port (7); a first rectifying unit (12) connected to the first stage input (14) and connected to a first stage output (16); a second rectifying unit (18) connected to the second stage input (15) and connected to a second stage output (17). Also provides is a trimming capacitor arrangement (30) and a first auxiliary rectifier stage (71) connected to the first antenna port (6), the second antenna port (7), the first stage output (16) and to the second stage output (17) and coupled to the trimming capacitor arrangement (30) to switch the trimming capacitor arrangement (30) into a predefined auxiliary configuration.

Abstract: A debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), including a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

Abstract: A system (10) including an energy harvesting circuit (12) connectable to an antenna (14) and configured to execute an autonomous matching procedure to match the antenna (14) to an electric load (15), a buffer capacitor (16) connected to the energy harvesting circuit (14) and chargeable by the energy harvesting circuit (14), and a control circuit (20) connected to the energy harvesting circuit (14) and to the buffer capacitor (16) and connectable to the electric load (15), wherein the control circuit (20) is configured to control a supply voltage of the electric load (15), and wherein the control circuit (20) comprises an auxiliary capacitor (22) chargeable during execution of the autonomous matching procedure.

Abstract: A method for applying illumination correction for an optical computer mouse, includes: flashing a light source of the mouse directed towards a surface; accumulating voltage on a pixel array of the mouse to obtain raw pixel values of an image frame in response to detecting light reflected from the surface; applying analog correction to the raw pixel values based on digital gain coefficients to obtain an array of corrected pixel values forming corrected image data; digitizing the corrected image data with an analog-to-digital converter to obtain digital pixel values forming digital image data; and updating the digital gain coefficients so that a gain coefficient corresponding to a digital pixel value is incremented if the digital pixel value is below or equal to a given pixel threshold value, and so that the gain coefficient is decremented if the digital pixel value is above the given pixel threshold value.

Abstract: An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

Abstract: A method, system, and computer program for modifying the configuration of a peripheral in a multi-clock domain system. The system includes a configuration/access interface operating on a first clock source signal and a data logic module with a data register operating on a second clock source signal. A configuration change detector identifies configuration updates, and a configuration manager synchronizes operations by dynamically disabling and enabling the second clock source based on the state of its signal. A data input controller updates the data register, with provisions for counter-based operations when applicable. The method ensures precise synchronization, minimizes latency, and maintains data integrity by automating operations within a single clock cycle of the first clock source signal. The invention is particularly suitable for real-time and embedded applications, where efficient resource utilization and reliable performance are critical.

Abstract: A data reading system including two clock sources (CS1 and CS2), a configuration/access interface (C/A-I), and various logic and register modules. The system includes a configuration/access logic module (C/A-L) that receives signals from CS1 and interfaces with the data logic module (DL). The data register module (DR) stores data and provides it to a data output register module (DOR), which generates a data output signal. The system features a read window generator (RWG) and a read manager (RM) to manage reading operations. The system operates in an idle or reading state, controlling data flow based on the state of the configuration/access interface.

Abstract: A charge amplifier circuit (10) for a capacitive sensing arrangement (80), the charge amplifier circuit (10) including: an first amplifier stage (20) including a first amplifier input (22), a second amplifier input (23) connectable to the capacitive sensing arrangement (80), and including a first amplifier output (24) and a second amplifier output (25), a second amplifier stage (30) including a first amplifier input (32), a second amplifier input (33), a first amplifier output (34) and a second amplifier output (35), and a switched capacitor arrangement (40) between the first amplifier stage (20) and the second amplifier stage (30), the switched capacitor arrangement (40) including a first integration capacitor (42), a second integration capacitor (43), a number of first switches (66, 67) and a number of second switches (68, 69).

Abstract: A switched resonant capacitor including a first capacitor and a second capacitor connected in series by means of a first switching element between a first conductor and a second conductor; the switched resonant capacitor further including a second switching element connected in parallel to the first capacitor and a third switching element connected in parallel to the second capacitor.

Abstract: An electronic circuit (10) for an optical motion sensing device (1), including: a processor (18) and a storage (16); an image acquisition unit (11) configured to store a reference image (12) and a current image (13) to be compared with the reference image (12); a correlation engine (14) configured to determine a correlation coefficient between the reference image (12) and the current image (13) for each displacement between the reference image (12) and the current image (13); and a search engine (15) for comparing the correlation coefficient of each displacement with a predefined threshold correlation coefficient. The search engine (15) is operable in one of a preliminary search mode and an accurate search mode, and when in the accurate search mode, the search engine (15) is configured to store the correlation coefficient obtained from the correlation engine in the storage (16).

Abstract: A computer mouse and a computer-implemented method for operating a computer mouse. The method includes: calculating a first/tracking optical sensor flash rate, generating tracking flashes in order identify relative displacement along an underlying surface, calculating a second/surface optical sensor flash rate taking into account the first/tracking optical sensor flash rate, and generating surface flashes in order identify surface characteristics along the underlying surface, so that a surface flash is generated between two tracking flashes.

Abstract: A dual communication frequency RFID circuit (10) including: a first logic unit (13) for processing data signals received or transmitted by a first frequency by a first antenna (11), a second logic unit (14) for processing data signals received or transmitted by a second frequency by a 1 second antenna (12), a shared memory unit (15) connected to the first logic unit (13) and connected to the second logic unit (14) and including a shared password storage section (20) accessible by the first logic unit (13) and by the second logic unit (14).

Abstract: A computer-implemented method for operating an electronic device including a microcontroller and an optical sensor generating flashes along an underlying surface. The method includes: calculating a surface optical sensor flash rate; generating surface flashes in order to acquire an associated image having pixels and identify surface characteristics along the underlying surface; and classifying surface characteristics comprising a method of comparing a ripple of the average light detected per pixel to a threshold.

Abstract: An impedance matching network (10) for an active RFID transceiver (1), the impedance matching network (10) including: an impedance transformer (14) including a transformer input (13) and a transformer output (15), wherein the transformer input (13) is connectable to an antenna (12), an RF modulator (16) connectable to the transformer output (15), and an RF demodulator (20) capacitively coupled to the transformer output (15) via a capacitor (18).

Abstract: A voltage limiter for a signal receiver (1), the voltage limiter (20) including: an input (21) connectable to a signal source (10); an output (22) connectable to a detector (70) and connected to the input (21) via a signal conductor (30); a ground conductor (40) connectable to ground (5); a first branch (24) connected to the signal conductor (30), connected to the ground conductor (40) and comprising a first diode element (52); a second branch (25) connected to the signal conductor (30), connected to the ground conductor (40) and comprising a second diode element (53); and a resistor element (36, 54, 55) between the signal conductor (30) and the ground conductor (40).