Abstract: An embodiment of the invention relates to a method for sensing a displacement of a pointing device, like a mouse. The pointing device includes at least one light source configured to illuminate a surface, at least one first secondary photodetector, at least one second secondary photodetector and at least one primary photodetector. Each individual value of photodetectors is weighted and compared to sense the displacement of the pointing device by comparing a plurality of storage elements.

Abstract: A skin contact sensing device (10) including a contact sensor (11) operable to generate electrical contact signals being indicative of a skin contact; a processor (12) connected to the contact sensor (11) and operable to process the electrical contact signals received from the contact sensor (11); and a memory (15) connected to the processor (12) and operable to store at least one calibration parameter, wherein the processor (12) is operable to ascertain a skin contact by processing of the electrical contact signals on the basis of the at least one calibration parameter and wherein the processor (12) is operable to read and to obtain the at least one calibration parameter from the memory (15).

Abstract: An electronic device including a Bluetooth communication unit configured to perform Bluetooth communication, this unit including a memory module containing a memory controller and a memory element equipped with at least one page (P) including at least one encoded data (E) including a binary code being formed by a word (W 0-N) and its associated redundancy code (RC 0-N), the memory controller being configured to store a user data in this page (P) by performing error correction code (ECC) calculations on this user data for providing an associated redundancy code (RC 0-N) corresponding to an erased redundancy code (RC E) for this user data, if this user data has a reference binary code of an erased word (W E), the erased redundancy code (RC E) having a binary value similar to that of the reference binary code.

Abstract: A method for managing data stored in a page (P) within a memory element of a memory system including a controller, the page (P) including at least one encoded data (E) consisting in a binary code being formed by a word (W 0-N) and its associated redundancy code (RC 0-N), the method including a step of storing a user data in this page (P) implemented by the controller, this step including a sub-step of performing error correction code (ECC) calculations on the user data providing an associated redundancy code (RC 0-N) corresponding to an erased redundancy code (RC E) for this user data if it has a reference binary code (br) of an erased word (W E) the erased redundancy code (RC E) having a binary value similar to that of the reference binary code (br).

Abstract: A system with a low-drift on-chip (LD-RC) oscillator with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator. A control resistor (R) is connected through an intermediary arrangement to one of a first MOS transistor (M1) or of a second MOS transistor (M2) between two terminals of a supply voltage source (Vdd). The gate of the first MOS transistor (M1) is connected to the gate of the second MOS transistor (M2), whereas the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source.

Abstract: A method to produce an integrated circuit including depositing a first layer of a metallic chemical constituent on a silicon substrate. A protective layer including a main chemical constituent different from the main chemical constituent of the first layer is then deposited on this first layer. An additional layer is deposited on the protective layer and includes a main chemical constituent different from, equivalent to or of equivalent size to the main chemical constituent of the first layer. A heat treatment operation is carried out at a first temperature to generate a silicide including the main constituent of the first layer and silicon according to a first stoichiometry. In a subsequent step, the additional layer and the protective layer are removed. In another step, a further heat treatment operation is carried out at a temperature greater than the first temperature in order to change the stoichiometry of the previously created silicide.

Abstract: A method for reading data from a non-volatile memory array including a plurality of memory cells, each configured to store one bit of information. The method includes the steps of: powering on the memory array, where information from at least a first memory cell and a second memory cell is collectively associated with one bit of sensible data; b) reading a first memory cell value and a second memory cell value by comparing a reference value to a respective electrical property value of the respective memory cell to determine the respective memory cell value; c) adjusting the reference value in the event at least the first and second memory cell values have a first combination of logic state values to obtain an adjusted reference value; d) reading the first and second memory cell values by using the adjusted reference value to obtain a second combination of logic state values; and e) determining a sensible data bit value based on the obtained second combination of logic state values.

Abstract: An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

Abstract: A clock distribution network (10) including a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator including a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42). A first peripheral unit (22) via a first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).

Abstract: A digital logic controller including a first delay cell connectable to a signal input and operable to generate a first time delayed input signal, a second delay cell connectable to the signal input and operable to generate a second time delayed input signal, a counter connectable to the signal input via the first delay cell, two logic units to generate reset signal by one of logic units and to generate set signal by the other of logic units, and connected between the set of delay cells and a flip-flop operable to generate a counter valid signal at a flip-flop output, a first comparator connected to an output of the counter and operable to compare a counter output signal with a first target, a first logic gate connected to the flip-flop output, connected to the first comparator and operable to temporally deactivate processing of the counter output signal.

Abstract: A sealed electronic module (1) including at least one actionable part (2), the module (1) including a case (2) having: a watertight compartment (4) containing a printed circuit board (5), the compartment (4) being formed by a housing (13) with a unique opening (20), the housing (13) including the printed circuit board (5), and a sealing element (6a, 6b) configured for closing tightly the unique opening (20) by being fixed to the housing (13) and the printed circuit board (5).

Abstract: A wearable device (1) including a case (2a, 2b) including a watertight compartment (26) containing a printed circuit board (5), the case (2a, 2b) being assembled to a strap (4a, 4b) for mounting this wearable device (1) on a body part of a user, said assembly of the case (2a, 2b) with the strap (4a, 4b) being configured so that a portion (7) of this strap (4a, 4b) includes at least one actionable part of the device (1).

Abstract: A displacement detection circuit (100) configured to implement a displacement detection method (500) for a pointing device (199) having at least one pixel array (190). The displacement detection circuit (100) includes at least one main calculator (110), at least one auxiliary calculator (111, 112, 113) at least one comparator (130) and at least one motion detector (150). The main calculator (110) is configured to calculate at least one main average (210) corresponding to the average of the at least one pixel array (190), which is compared to at least one auxiliary average (211, 212, 213) of the at least one auxiliary calculator (111, 112, 113). According to the result of the comparison, the at least one motion detector (150) indicates at least one direction (250) of displacement of the pointing device (199).

Abstract: A semiconductor wafer (1a, 1b) including a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).

Abstract: A method for applying illumination correction for an optical computer mouse, includes: flashing a light source of the mouse directed towards a surface; accumulating voltage on a pixel array of the mouse to obtain raw pixel values of an image frame in response to detecting light reflected from the surface; applying analog correction to the raw pixel values based on digital gain coefficients to obtain an array of corrected pixel values forming corrected image data; digitizing the corrected image data with an analog-to-digital converter to obtain digital pixel values forming digital image data; and updating the digital gain coefficients so that a gain coefficient corresponding to a digital pixel value is incremented if the digital pixel value is below or equal to a given pixel threshold value, and so that the gain coefficient is decremented if the digital pixel value is above the given pixel threshold value.

Abstract: In a sensing device of a pointing device, like a mouse, said pointing device includes at least one light source configured to illuminate a surface, at least one first secondary photodetector, at least one second secondary photodetector, and at least one primary photodetector. Each individual storage element of photodetectors is weighted and compared such as to sense a displacement of the pointing device.

Abstract: In a method for sensing a displacement of a pointing device, like a mouse, said pointing device includes at least one light source configured to illuminate a surface, at least one first secondary photodetector, at least one second secondary photodetector, and at least one primary photodetector. Each individual value of the photodetectors is weighted and compared such as to sense said displacement of the pointing device.

Abstract: An output driver (12), including: a first supply rail (13A) configured to receive a high supply electrical voltage (Vdd); a second supply rail (13B) configured to receive a low supply electrical voltage (Vss); a pad terminal (15) configured to output an output electrical voltage (V_pad_out); an output stage (14) connected to the pad terminal (15) and to the first and second supply rails (13A, 13B). The output stage (14) has an electrical clamping circuit (18A, 18B) including a semiconductor electronic switching component (Q3, Q6) made of a first type of semiconductors and a semiconductor electronic switching component (Q4, Q7) made of a second type of semiconductors. A resistor (R3, R0) is connected between the first or second supply rail and the semiconductor electronic switching component (Q3, Q6) of the first type, at an intermediate terminal (20, 24).

Abstract: A power control unit is provided to control the efficiency of a charge pump converter having a first input terminal and a second input terminal, a primary attenuator and a secondary attenuator between a first input terminal and the second input terminal, a first output terminal, a second output terminal, a secondary attenuator controlling terminal and a primary attenuator controlling terminal to be plugged to the power control unit. The primary attenuator controlling terminal and the secondary attenuator controlling terminal are to attenuate or amplify a signal of the first input terminal and the second input terminal.

Abstract: A voltage limiter for a signal receiver (1), the voltage limiter (20) including: an input (21) connectable to a signal source (10); an output (22) connectable to a detector (70) and connected to the input (21) via a signal conductor (30); a ground conductor (40) connectable to ground (5); a first branch (24) connected to the signal conductor (30), connected to the ground conductor (40) and comprising a first diode element (52); a second branch (25) connected to the signal conductor (30), connected to the ground conductor (40) and comprising a second diode element (53); and a resistor element (36, 54, 55) between the signal conductor (30) and the ground conductor (40).