Abstract: The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Abstract: An electronic device including: a calculation unit configured to generate a signal representative of a physical magnitude, for a motor driving a display device, the motor including two terminals, one positive and one negative, via which the calculation unit controls the motor; at least one shock detection circuit connected between the calculation unit and one terminal of the motor for detection of an external shock applied to the motor. The shock detection circuit includes a comparison part comparing an induced voltage generated in the motor following a shock to a predetermined reference voltage to identify a shock, and a selection part.

Abstract: The present invention concerns a method of operating a first-in first-out memory (9) arranged to store measurement data samples measured by a plurality of data measurement sensors (1, 3, 5), which can operate at various sampling rates. The oldest measurement data sample in the memory (9) is arranged to be read first before the newer measurement data samples. The method comprises: receiving measurement data samples from at least two data measurement sensors (1, 3, 5); and saving the received measurement data samples in the memory (9). Each of the measurement data samples saved in the memory is associated with a tag which is also saved in the memory (9) and which identifies the data measurement sensor (1, 3, 5) which measured the respective measurement data sample.

Abstract: A memory circuit is provided, including at least one bit cell configured to store data and having a first terminal and a second terminal, one of the terminals being coupled to a bit-line; at least one current switch connected to the bit-line and connected to a current source and being configured to selectively provide at least a read current to the bit cell; and a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is disposed between the bit cell and the at least one current switch.

Abstract: A DC-DC converter (1) with low start-up power and voltage includes an inductor (3) connected to an input voltage source (2), a switch (11) connected to the inductor and controlled by a controller (10) and a diode (12) connected to a connection node of the inductor and the switch to provide an output voltage (Vout). The controller includes an oscillator and a monostable element, which are powered by the input voltage (Vin). The oscillator provides an oscillation signal (OSC) having a period T of a switching cycle of the switch. The monostable element (103) is controlled by the oscillation signal to determine a duration Tn of conduction of the switch, during which an increasing current (IL) flows through the inductor. The input impedance of the DC-DC converter increases, when the input voltage (Vin) drops below a first voltage threshold with a decreasing duty cycle d=Tn/T.

Abstract: A communication beacon including a calculation unit associated with a memory module for data storage and with a communication circuit, the beacon being powered by a power unit, the communication circuit including a first interface unit using a first protocol, a second interface unit using a second protocol, the memory unit including a first memory unit and a second memory unit each memory unit being electrically connected to each interface unit.

Abstract: The smart battery (1) includes an electronic module provided with an electronic circuit (8) for controlling the supply voltage, which is disposed in a case having a cover (2) as the external negative terminal, fixed to a cup (3), as the external positive terminal. A first chemical substance (4) as the anode and a second chemical substance (5) as the cathode, are inside the case. The electronic module includes a printed circuit board (7) having a first face with conductive paths, connected to the electronic circuit, and a second insulating face fixed to the second chemical substance. The electronic circuit is connected at output to a first connection pad connected to the cup. The electronic circuit is connected to the chemical substances by a second connection pad on a first tab (7?) and by a third connection pad on a second tab (7?) folded at 180° on the second face of the printed circuit board.

Abstract: A method for transmitting a beacon message, the method generating, with a beacon generating device at least one beacon message, wherein the at least one beacon message is defined by a beacon message format, wherein the beacon message format comprises a preamble field, an access address field, a protocol data unit (PDU) field and a cyclic redundancy check (CRC) field, wherein the PDU field comprises at least one electronic product code (EPC) encoded EPC-PDU field, and transmitting, with the beacon generating device, the at least one beacon message using a Bluetooth Low Energy (BLE) wireless communication protocol to a transmission area within a transmission range of the beacon generating device for reception by one or more beacon receiving devices located in the transmission area.

Abstract: The time base includes an oscillator generating a periodic signal, a frequency divider circuit formed by a division chain defining several division stages and a circuit for adjusting the divided frequency by inhibiting, in each inhibition period of a plurality of successive inhibition periods, an integer number of clocking pulses at the input of a given stage of the division chain. The time base is arranged to produce, in each inhibition period, a first real number corresponding to the real number of clocking pulses that must be removed to be precise and the adjustment circuit is arranged to calculate, in each inhibition period, a second real number equal to the addition of the first real number and the fractional part of the second real number obtained in the preceding inhibition period, the integer part of this second real number defining the number of clocking pulses to be inhibited in each inhibition period.

Abstract: A half-duplex passive transponder including: a resonant circuit including an antenna and input capacitor and configured to allow an electrical signal to oscillate in the resonant circuit when periodically receiving across the antenna an activation signal from a reader; at least one switch between the input capacitor and a storage capacitor so the two capacitors are in parallel when the switch is turned on; a peak voltage detector configured to measure amplitude of the electrical signal oscillating in the resonant circuit; and a variable voltage threshold determination circuit configured to trigger each of plucking pulses when voltage of the oscillating electrical signal substantially attains a variable voltage threshold in a respective period before an extremum of the oscillating electrical signal and in a half-cycle of the extremum, to thus deliver plucking pulses during a transmission period in the resonant circuit to maintain a certain amplitude of the oscillating electrical signal.

Abstract: The motor driver of an horological motor consumes an important part of the electrical energy of the electronic circuit due to the fact that configuration data has to be transferred to configuration registers before each turn/step. In order to reduce the power consumption a circuitry is proposed, which detects a change in at least one of the configuration registers. This detection is used to trigger a refresh of the configuration registers only when actually a change in at least one of these configuration registers occurs.

Abstract: The present invention relates in one aspect to an auxiliary charge pump for a RFID rectifier, the charge pump, which comprises a first charge pump stage (11; 111) connected to an input (14; 114), a second charge pump stage (12; 112) connected to the input, a diode clamp (13; 113) connected to an output (15; 115), and a regulating transistor (16; 116) having a gate connected with an output (21; 121) of the first charge pump stage and having a source and a drain, wherein one of the source and the drain is coupled to the diode clamp. In further aspects the invention relates to a RFID transponder, to a multistage rectifier and to a rectifier stage comprising such an auxiliary charge pump.

Abstract: The present invention relates to a transponder, which comprises an antenna and a multi-stage rectifier. The antenna is connected to an input of the multi-stage rectifier having m rectifier stages, and a shunt limiter is connected to an output of the rectifier and connected to an nth stage of the multi-stage rectifier, wherein n<m.

Abstract: The invention concerns a method and device for processing UHF signals for an EPC communication. The method includes the steps of picking up UHF signals by an antenna of the device for processing UHF signals, creating an envelope signal from the UHF signals picked by the antenna in a demodulator, processing the envelope signal and decoding critical TRcal symbol and data in a logic unit of the device. Furthermore, the method includes the steps of interpreting the critical TRcal symbol and data, storing the interpreted data, encoding transmit data, modulating by encoded data in a modulator, and clocking the steps as above by a local oscillator. In the step of processing the envelope signal, the critical TRcal symbol is processed by a high frequency clock and data are processed by a low frequency clock.

Abstract: A fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly includes a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes includes a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.

Abstract: A circuit (1) is described for detecting a reverse current condition of a DCDC converter (2). This circuit uses a simple logic gate such as an AND gate to sense the voltage on a determined node (7) of the DCDC converter, and the propagation of the gated signal (27) is controlled using the timing control signals SW1 and SW2 of the DCDC converter, together with delay cells (16 and 17), to ensure that the positive or negative state of the sensed voltage at said node (7) is propagated cleanly through the logic gate (18), the flip-flop or latch circuit (19) and the up-down counter (29) to the output timing control circuit (25). The up-down counter is incremented or decremented in dependence on the presence or absence of a reverse current condition at said node, and the count value (24) of the up-down counter determines the duration of the on-period of the second-phase timing control signal SW2.

Abstract: The electronic circuit measures angular speed in a gyroscope, which includes a mass connected to a spring and a damping element, an actuation capacitor for actuating the mass and a detection capacitor for detecting motion of the mass. The electronic circuit includes a measurement resistor, which is connected to the moving mass and has a variation in resistive value equal to the oscillation frequency of the mass. The resistor is polarized to supply a measurement signal, which includes a carrier signal in phase with the oscillation of the mass and an angular speed signal phase shifted by ?/2 relative to the carrier signal The measurement signal is supplied to an integration unit clocked by a clocking signal phase shifted by ?/2 relative to the carrier signal and originating from the drive circuit. The angular speed signal is demodulated at the integration unit output.

Abstract: The present invention relates to a memory circuit comprising: at least one bit cell for storing data and having a first terminal and a second terminal, wherein one of said terminals is coupled to a bit-line, at least one current switch connected to the bit-line and connected to a current source and being operable to selectively provide a current to the bit cell, a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is located between the bit cell and the at least one current switch.

Abstract: The invention concerns a multi-frequency transponder for communicating at a first frequency according to a first communication protocol and at a second different frequency according to a second communication protocol. The transponder comprises a first physical memory for storing a first data of the first communication protocol; a second physical memory for storing a second data, different from the first data, of the second communication protocol; and a logic unit for accessing the first and second physical memories. The logic unit comprises a first control unit for handling communications according to the first protocol, and a second control unit for handling communications according to the second protocol. The transponder comprises a mapping memory to store a logical memory map of the first or second physical memories. The logical memory map comprises mapping information for the first or second control unit to access data items in first and second physical memories.

Abstract: The invention relates to a measuring circuit comprising a control block for controlling said circuit, a time base for providing a clock signal (fclk) in order to time said circuit, a sensor block which is designed to provide an output signal, said measuring circuit comprising in addition a first counting block which is timed to the clock frequency and a second counting block which is timed by the frequency of the output signal of the sensor block.