Abstract: The method is for measuring a physical parameter by an electronic circuit connected to a two differential capacitor sensor having two fixed electrodes and a common moving electrode. The electronic circuit supplies first and second digital measuring signals. Each measuring cycle consists on biasing the electrodes by the measuring voltage based on the first digital signal, connecting the fixed electrodes to a supply voltage source for a first biasing, biasing the electrodes by the measuring voltage based on the second digital measuring signal, and inversely connecting the fixed electrodes to a supply voltage source for a second biasing. In first successive measuring cycles, the first and second digital signals are adapted to each cycle by a large step value. In second successive measuring cycles, the first and second digital signals are adapted to each cycle by a small step value until the end of the conversion.

Abstract: The electronic circuit measures angular speed in a gyroscope, which includes a mass connected to a spring and a damping element, an actuation capacitor for actuating the mass and a detection capacitor for detecting motion of the mass. The electronic circuit includes a measurement resistor, which is connected to the moving mass and has a variation in resistive value equal to the oscillation frequency of the mass. The resistor is polarized to supply a measurement signal, which includes a carrier signal in phase with the oscillation of the mass and an angular speed signal phase shifted by ?/2 relative to the carrier signal The measurement signal is supplied to an integration unit clocked by a clocking signal phase shifted by ?/2 relative to the carrier signal and originating from the drive circuit. The angular speed signal is demodulated at the integration unit output.

Abstract: The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.

Abstract: Method for reading a barcode by means of an optical reader arranged to capture at a determined sampling frequency a series of partial images of the barcode by a sensor having at least one line of pixels. According to the invention it is provided to determine in each partial image a logical value as a function of the light intensity received by a central pixel of the line of pixels and a corresponding bar width when this bar is completely incorporated into the partial image in question. By only setting a maximum speed for the speed of movement of the barcode and dimensioning the line of pixels to ensure that each bar of this barcode is completely incorporated into a partial image at least once, the sequence of bits defined by the barcode is determined by means of an algorithm ignoring the duplications detected in consecutive partial images.

Abstract: A circuit (1) is described for detecting a reverse current condition of a DCDC converter (2). This circuit uses a simple logic gate such as an AND gate to sense the voltage on a determined node (7) of the DCDC converter, and the propagation of the gated signal (27) is controlled using the timing control signals SW1 and SW2 of the DCDC converter, together with delay cells (16 and 17), to ensure that the positive or negative state of the sensed voltage at said node (7) is propagated cleanly through the logic gate (18), the flip-flop or latch circuit (19) and the up-down counter (29) to the output timing control circuit (25). The up-down counter is incremented or decremented in dependence on the presence or absence of a reverse current condition at said node, and the count value (24) of the up-down counter determines the duration of the on-period of the second-phase timing control signal SW2.

Abstract: The present invention concerns an electronic circuit comprising a control signal processing circuit with a control signal input and a control signal output circuit, the processing circuit being arranged to process a control signal applied to the control signal input, and to operate in at least one of a first power mode and a second power mode, the second power mode having a lower power consumption than the first power mode. The electronic circuit further comprises a control signal processing circuit bypass means for providing, when the processing circuit is in the second power mode, a bypass connection for conveying the control signal from the control signal input to the control signal output circuit, thereby bypassing the processing circuit.

Abstract: A method adjusts a reference voltage of an electronic circuit based on a band-gap voltage supplied by a first band-gap stage. The band-gap stage includes in a series arrangement, between two terminals of a voltage supply source, a current source connected to a first branch, which includes a first configurable resistor in series with a first diode, and to a second branch, which includes a second configurable resistor connected to a complementary resistor in series with a second diode. The band-gap voltage is supplied to a connection node between the current source and each branch. The current source is a PMOS transistor controlled by an output voltage of a first operational amplifier of a current control loop.

Abstract: The invention relates to a procedure for accessing a non-volatile watch memory, the watch comprising two supply terminals accessible from the outside that define a potential difference corresponding to a standard supply voltage, and a control circuit of the non-volatile memory produced using a technology supporting a predefined maximum supply voltage, the access procedure consisting of transmitting the following to the control circuit of the non-volatile memory by means of a supply terminal of the watch: a) an opening key to authorize access to the non-volatile memory; b) an instruction for access to the non-volatile memory; the procedure being characterized in that the opening key is a predefined instruction transmitted by modulation of the standard supply voltage such that this does not exceed the predefined maximum supply voltage.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises: a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: The random number generator comprises a linear feedback shift register (10), which comprises a series of storage elements (14(1), 14(2), . . . , 14(n)), a first input (11) to receive a clock signal from a clock oscillator (28), a feedback line (20) connecting the output of a last storage element (14(n)) with an input of at least a first storage element (14(1)), a second input (22) coupled with the feedback line (20) via at least one cell (15) and wherein the output of the cell (15) is coupled to an input of at least one of the storage elements (14(1), 14(2), . . . , 14(n)).

Abstract: The electronic circuit (1) is for driving a resonator (2) of a MEMS resonator device. The resonator includes a mass (m) connected to a spring (k) and a damping element (d), an actuation element (Cact) for actuating the mass via an actuation signal (drive), and a detection element (Cdet) for detecting motion of the mass. The electronic circuit includes a conversion means (3) connected to the detection element to supply a mass oscillation derivative signal (der), a means (4, 5, 6) of comparing the derivative signal amplitude and a reference amplitude (ref) for supplying a control signal (cmd), and a decision unit (7) for supplying a digital actuation signal (drive). The actuation signal includes rectangular pulses determined on the basis of the derivative signal and of the control signal to adapt the mass oscillation amplitude according to the reference amplitude.

Abstract: Method for reading a barcode by means of an optical reader arranged to capture at a determined sampling frequency a series of partial images of the barcode by a sensor having at least one line of pixels. According to the invention it is provided to determine in each partial image a logical value as a function of the light intensity received by a central pixel of the line of pixels and a corresponding bar width when this bar is completely incorporated into the partial image in question. By only setting a maximum speed for the speed of movement of the barcode and dimensioning the line of pixels to ensure that each bar of this barcode is completely incorporated into a partial image at least once, the sequence of bits defined by the barcode is determined by means of an algorithm ignoring the duplications detected in consecutive partial images.

Abstract: The circuit is provided for the transmission of data amplitude modulated radio frequency signals. The circuit includes a local oscillator for generating an oscillating signal at a determined carrier frequency, a unit for shaping data pulses to supply a data amplitude modulation control signal (Vmod), and a power amplifier receiving the oscillating signal and the data amplitude modulation control signal (Vmod) for the transmission of data amplitude modulated radio frequency signals by an antenna or an antenna arrangement. The data pulse shaping unit (13) includes a pulse shaper (21) for digitally adapting the data transition edges on the basis of an incoming digital data signal (d), and a digital-analog conversion stage (26, 27) for converting a digital data signal shaped in the unit, in order to supply the data amplitude modulation control signal (Vmod) to the power amplifier.

Abstract: The invention relates to a measuring circuit comprising a control block for controlling said circuit, a time base for providing a clock signal (fclk) in order to time said circuit, a sensor block which is designed to provide an output signal, said measuring circuit comprising in addition a first counting block which is timed to the clock frequency and a second counting block which is timed by the frequency of the output signal of the sensor block.

Abstract: The present invention relates to a narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver comprises an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.

Abstract: Process for adjusting a time base by inhibiting clock pulses supplied by a clock circuit, this adjustment process comprising the following steps: selecting an inhibition period; determining a first number N of clock pulses to be suppressed per inhibition period to adjust over each inhibition period the number of clock pulses activating a frequency divider circuit such that the frequency of the time base comes closest to a reference unit frequency; selecting a plurality K of sub-periods for each inhibition period; suppressing in each sub-period a second number N1 of clock pulses corresponding to the result of the integral division of the first number by the number of sub-periods, and in addition to the suppression of the preceding step, suppressing in each inhibition period a third number N2 of clock pulses corresponding to the remainder of said integral division.

Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract: A half-duplex passive transponder including: a resonant circuit including an antenna and input capacitor and configured to allow an electrical signal to oscillate in the resonant circuit when periodically receiving across the antenna an activation signal from a reader; at least one switch between the input capacitor and a storage capacitor so the two capacitors are in parallel when the switch is turned on; a peak voltage detector configured to measure amplitude of the electrical signal oscillating in the resonant circuit; and a variable voltage threshold determination circuit configured to trigger each of plucking pulses when voltage of the oscillating electrical signal substantially attains a variable voltage threshold in a respective period before an extremum of the oscillating electrical signal and in a half-cycle of the extremum, to thus deliver plucking pulses during a transmission period in the resonant circuit to maintain a certain amplitude of the oscillating electrical signal.

Abstract: The invention concerns a test method for a transmitter-receiver circuit. This transmitter-receiver circuit includes an antenna, connected to a processing unit, arranged for receiving signals and converting their frequency. The transmitter-receiver circuit also includes a power amplifier connected to said antenna and arranged for sending transmission signals.