Patents Assigned to Entorian Technologies, LP
  • Patent number: 7804985
    Abstract: Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: September 28, 2010
    Assignee: Entorian Technologies LP
    Inventors: Leland Szewerenko, Julian Partridge, Ron Orris
  • Patent number: 7759791
    Abstract: A system and method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: July 20, 2010
    Assignee: Entorian Technologies LP
    Inventors: Julian Partridge, Leland Szewerenko, James Douglas Wehrly, Jr.
  • Patent number: 7760513
    Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The rigid substrate exhibits adhesion features that allow more advantageous use of thermoplastic adhesives with concomitant rework advantages and while providing flexibility in meeting dimensional specifications such as those promulgated by JEDEC, for example.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: July 20, 2010
    Assignee: Entorian Technologies LP
    Inventors: Julian Partridge, David Roper, Paul Goodwin
  • Patent number: 7737549
    Abstract: Flexible circuitry is populated with integrated circuitry (ICs), and contacts are distributed along the flexible circuitry to provide connection to an application environment. The flexible circuitry is disposed about a rigid substrate, placing the ICs on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate is preferably devised from thermally-conductive materials and one or more thermal spreaders are in thermal contact with at least some of the ICs. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: June 15, 2010
    Assignee: Entorian Technologies LP
    Inventors: James Douglas Wehrly, Jr., James Wilder, Mark Wolfe, Paul Goodwin
  • Patent number: 7719098
    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and an integrated circuit. In a two-high stacked circuit module devised in accordance with a preferred embodiment of the present invention, an integrated circuit is stacked above a precursor assembly. The two integrated circuits are connected with the flex circuit of the precursor assembly. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: May 18, 2010
    Assignee: Entorian Technologies LP
    Inventor: James Douglas Wehrly, Jr.
  • Patent number: 7675155
    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 9, 2010
    Assignee: Entorian Technologies, LP
    Inventor: Julian Partridge
  • Patent number: 7656678
    Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to additional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: February 2, 2010
    Assignee: Entorian Technologies, LP
    Inventors: Julian Partridge, James Douglas Wehrly, Jr., David L. Roper, Joseph Villani
  • Patent number: 7626259
    Abstract: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: December 1, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James Douglas Wehrly, Jr., James Wilder, Paul Goodwin, Mark Wolfe
  • Patent number: 7616452
    Abstract: Provided circuit modules employ flexible circuitry populated with integrated circuitry (ICs). The flex circuitry is disposed about a rigid substrate. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. A strain relief portion of the flex circuitry has preferably fewer layers than the portion of the flex circuitry along which the integrated circuitry is disposed and may further may exhibit more flexibility than the portion of the flex circuit populated with integrated circuitry. The substrate form is preferably devised from thermally conductive materials.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: November 10, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James Douglas Wehrly, Jr., Paul Goodwin, Russell Rapport
  • Patent number: 7608920
    Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 27, 2009
    Assignee: Entorian Technologies, LP
    Inventor: James Douglas Wehrly, Jr.
  • Patent number: 7606042
    Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: October 20, 2009
    Assignee: Entorian Technologies, LP
    Inventor: Paul Goodwin
  • Patent number: 7606049
    Abstract: A circuit module shunts thermal energy into a chassis component or a part of the box of the computing application in which the module is employed. In one preferred mode, a flex circuit is populated along each of its first and second major sides with two ranks of ICs which are, preferably, array type (CSP) devices. Insertion contacts are disposed in two sets on the first side of the flex circuit typically between the two ranks of ICs along the first side of the IC. A substrate with first and second lateral sides provides a form for the module. That substrate is preferably comprised of metallic material and exhibits an edge about which the flex circuit is wrapped and an extension at the other extremity of the substrate that is thermally connected to a chassis component of the application, either directly or, preferably, through a thermal conduit such as a thermally conductive compliant material.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 20, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Paul Goodwin, James W. Cady
  • Patent number: 7606040
    Abstract: Memory module flex circuitry is devised to accommodate packaged integrated circuit devices (ICs) of varying heights or thicknesses. The invention may be employed to advantage in a variety of modules that employ flex circuitry including, but not limited to, fully-buffered, registered or more simple memory modules. Many such modules may replace conventionally-constructed DIMMs without change to the system in which the module is employed. Regions of the flex circuitry devised to provide one or more mounting locales for ICs are delineated, in part, from the main body of the flex circuit. The delineation may be implemented in a preferred embodiment by separating a designated IC mounting area or peninsula from the main body of the flex circuitry either with isolating areas or separations or with tabs that extend from the primary perimeter of the flex circuitry.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: October 20, 2009
    Assignee: Entorian Technologies, LP
    Inventor: Paul Goodwin
  • Patent number: 7605454
    Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allowed the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: October 20, 2009
    Assignee: Entorian Technologies, LP
    Inventor: James Douglas Wehrly, Jr.
  • Patent number: 7606050
    Abstract: A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: October 20, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James W. Cady, James Douglas Wehrly, Jr., Paul Goodwin
  • Patent number: 7602613
    Abstract: A flexible circuit has contacts for mounting in a socket or card edge connector. The flexible circuit includes integrated circuit devices mounted on both sides of the edge connector contacts. Preferably, the flexible circuit is wrapped about an edge of a rigid substrate and presents contacts on both sides of the substrate for mounting in a socket. Multiple flexible circuits may be overlaid with the same strategy. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: October 13, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Paul Goodwin, James W. Cady, Douglas Wehrly
  • Patent number: 7595550
    Abstract: A form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design that is disposed about the form. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: September 29, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
  • Patent number: 7586758
    Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: September 8, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James W. Cady, James Wilder, David L. Roper, Russell Rapport, James Douglas Wehrly, Jr., Jeffrey Alan Buchle
  • Patent number: 7579687
    Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: August 25, 2009
    Assignee: Entorian Technologies, LP
    Inventors: Leland Szewerenko, Julian Partridge, Wayne Lieberman, Paul Goodwin
  • Patent number: RE41039
    Abstract: A stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface is a first conductive pad array, while disposed on the bottom surface is a second conductive pad array and third and fourth conductive pad arrays which are positioned on opposite sides of the second conductive pad array and electrically connected thereto. The chip package further comprises an integrated circuit chip which is electrically connected to the first and second conductive pad arrays, and hence to the third and fourth conductive pad arrays. The substrate is wrapped about at least a portion of the integrated circuit chip such that the third and fourth conductive pad arrays collectively define a fifth conductive pad array which is electrically connectable to another stackable integrated circuit chip package.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: December 15, 2009
    Assignee: Entorian Technologies, LP
    Inventor: John A. Forthun