Abstract: In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short channel effect (SCE) between the drain regions and the source region in the NOR flash memory.

Abstract: In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

Abstract: A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.

Abstract: In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract: A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time.

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.