Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material.

Abstract: Structure and method for temporarily holding at least one integrated circuit chip during packaging thereof are presented. A support plate has a release film secured to a main surface thereof. The support plate and release film allow UV light to pass therethrough. A UV curable chip adhesive is disposed over the release film for holding the at least one integrated circuit chip. After placement of the at least one integrated circuit chip in the UV curable chip adhesive, the UV curable chip adhesive is cured by UV light shone through the support plate and release film. As one example, the release film includes a UV release adhesive and the UV curable chip adhesive and UV release adhesive have a differential response to UV light which allows curing of the UV curable chip attach without release of the UV release adhesive.

Abstract: An interposer is provided which includes a PCB having compliant pins connected to a first surface of the PCB. A plurality of vias located in the PCB are connected to the compliant pins and extend from the first surface toward a second surface of the PCB. A method for making an interposer is also provided.

Abstract: A die package is provided including a circuit board with a recess for a die mounting area. A cap receiving area is located in the circuit board at least partially around the recess for the die mounting area. A cap located in the cap receiving area includes resilient contacts corresponding to at least some contact pad locations on one of a die or a secondary circuit board affixed to die to establish contact between the resilient contacts on the cap and the contact pad locations. A die for use with the die package can include contact pads in the heretofore unused center area of the die, as well as the typical peripheral contact pads, allowing more IO connections, more efficient connections and greater contact pad areas.

Abstract: An interposer and method for making same is disclosed. A metallic sheet is formed with a plurality of spring members. A first sheet of insulative material is provided on a top surface of the metallic sheet and a second sheet of insulative material is provided on a bottom surface of the metallic sheet. The insulative material sheets each include a plurality of flaps wherein each flap at least partially corresponds to a particular one of the spring members in the metallic sheet. A conductive material is located in a predefined pattern on the first and second insulative sheets having a conductive contact portion extending onto the flaps. Vias are connected to the conductive material and extend through metallic and insulative sheets to provide electrical connectivity.

Abstract: An electrical interposer including first and second surfaces is provided. A plurality of compliant pins are connected to the first surface of the substrate, each of the compliant pins having a drawn body with at least one side wall extending along a longitudinal axis thereof substantially perpendicular to the substrate. A plurality of contact elements are connected to the substrate for making electrical contact with a device facing the second surface of the substrate. Electrical paths connect the compliant pins to the contact elements.

Abstract: A method for making a contact begins by providing a sheet of material. A portion of the sheet is deep drawn to form a cavity having at least one sidewall, the cavity extending away from a rim formed by a non-drawn portion of the sheet. At least one spring member is defined from the at least one sidewall and is bent such that at least a portion of the at least one spring member extends beyond the rim.

Abstract: Structure and method for temporarily holding at least one integrated circuit chip during packaging thereof are presented. A support plate has a release film secured to a main surface thereof. The support plate and release film allow UV light to pass therethrough. A UV curable chip adhesive is disposed over the release film for holding the at least one integrated circuit chip. After placement of the at least one integrated circuit chip in the WV curable chip adhesive, the WV curable chip adhesive is cured by WV light shone through the support plate and release film. As one example, the release film includes a WV release adhesive and the WV curable chip adhesive and UV release adhesive have a differential response to UV light which allows curing of the WV curable chip attach without release of the UV release adhesive.

Abstract: An electrical connector for electrically connecting to pads of a land grid array formed on an electronic component includes a dielectric layer including opposing first and second surfaces, and a multiple number of contact elements extending above the first surface of the dielectric layer. Each contact element includes a conductive portion disposed to engage a respective pad of the land grid array for providing electrical connection to the land grid array. In particular, the multiple number of contact elements includes a first contact element and a second contact element whereby the first contact element has an operating property different than an operating property of the second contact element. In one embodiment, the operating property includes a mechanical or an electrical property. For example, the first contact element can have a larger elasticity than the second contact element.

Abstract: A connector for electrically connecting to pads of a land grid array formed on an electronic component includes a dielectric layer including opposing first and second surfaces, and a multiple number of contact elements extending above the first surface of the dielectric layer. Each contact element includes a conductive portion disposed to engage a respective pad of the land grid array for providing electrical connection to the land grid array. The connector further includes an electrical circuit formed on or within the dielectric layer. The electrical circuit is electrically connected to at least one of the multiple number of contact elements. In one embodiment, the electrical circuit includes an electrical component, such as a decoupling capacitor. In another embodiment, the electrical circuit operates to connect two contact elements together. For instance, the contact elements connecting to the ground potential can be connected together through the electrical circuit.

Abstract: Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure.

Abstract: Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure.

Abstract: Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure.

Abstract: Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric material is disposed on at least one of the first and second electrical structures. This dielectric material is a low modulus material which has a high ultimate elongation property (LMHE dielectric). Preferably, the LMHE dielectric has a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least 20 percent. The LMHE dielectric can be photo patternable to facilitate formation of via openings therein and a metal layer is formed above the LMHE dielectric which has conductors capable of expanding or contracting with the dielectric.

Abstract: Chips first packaging structures and methods of fabrication are presented which employ electroless metallizations. An electroless barrier metal is disposed over and in electrical contact with at least one aluminum contact pad of the chips first integrated circuit. The electroless barrier metal is a first electroless metal and is a different material than the at least one aluminum contact pad. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal. The electroless interconnect metal is a second electroless metal, which is different from the first electroless metal. As an example, the electroless barrier metal comprises electroless nickel and the electroless interconnect metal comprises electroless copper.

Abstract: Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper surface of the structural material are co-planar and the lower surface of at least one chip and a lower surface of the structural material are co-planar. A photo-patternable dielectric is disposed directly on the upper surfaces of the chips. The photo-patternable dielectric includes vias to at least some contact pads at the upper surfaces of the chips and the module further comprises an intrachip metallization layer on the photo-patternable dielectric layer. Subsequent processing provides a multi-layer chip interconnect structure over the intrachip metallization layer and photo-patternable dielectric.

Abstract: Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper surface of the structural material are co-planar and the lower surface of at least one chip and a lower surface of the structural material are co-planar. A photo-patternable dielectric is disposed directly on the upper surfaces of the chips. The photo-patternable dielectric includes vias to at least some contact pads at the upper surfaces of the chips and the module further comprises an intrachip metallization layer on the photo-patternable dielectric layer. Subsequent processing provides a multi-layer chip interconnect structure over the intrachip metallization layer and photo-patternable dielectric.

Abstract: A device is provided for sensing a condition of a non-rotating pneumatic tire preferably of the type used on an automobile wherein the tire is mounted on a tire rim. The device comprises a housing, a band for mounting the housing to the tire rim, a sensor for monitoring the condition within the tire, circuitry operatively connected to the sensor for generating radio signals indicative of the tire condition, a power supply operatively connected to the circuitry, an externally controlled switch, and a receiver for receiving the radio signals. The externally controlled switch is manually or electromagnetically operable to cause the condition sensor to generate radio signals when the pneumatic tire is stationary. A method of mathematically cross-linking data and identification information is provided to ensure data integrity. Also, the system includes a data logging capability for storing time series tire condition information for use as a historical log of tire use.