Abstract: An imager includes an array of imager cells coupled to a multi-mode controller. The multi-mode controller includes circuitry that implements several modes of operation, including a high-light mode, a low-light mode, and a Snap mode. The high-light mode provides charge accumulation in a photoreceptor potential well, a readout potential well, and a sense node potential well. The low-light mode provides charge accumulation in the photoreceptor potential well constrained by an integration potential well. The Snap mode of operation simultaneously transfers accumulated charge for a set of the imager cells to their sense nodes. In addition, the multi-mode controller may select one of a plurality of V+ integration voltages for setting up a selected charge capacity in one of the imager cells. Thus, the V+ integration voltage may be increased to provide charge capacity to address increased light levels.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network.

Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is disposed to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. During the integration period, the readout clock is at an integration voltage V+ which may be varied to setup a desired charge capacity in the photoreceptor. A thin gate structure or light aperture may be included to enhance blue light response of the photoreceptor. Thus, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.

Abstract: A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.

Abstract: A shared output visible imager pixel array combines a high optical fill factor with low read noise. A relatively small group of pixels are connected to a relatively short common bus line. An amplifier located in close proximity with the pixels is connected to the common bus line and shared among the pixels. By reducing the amount of amplifier circuitry associated with each pixel, the optical fill factor is increased. Also, since the bus line is relatively short, the bus capacitance is much lower relative to the traditional passive-pixel designs. On average, the transistor count per pixel can be less than two, for large arrays.

Abstract: A radiation receiving apparatus that comprises a pixel array and one or more microlenses located between the source of radiation and a less sensitive pixel in the pixel array. The arrangement of microlenses in a radiation receiving apparatus utilize a system architecture that recognizes that within a pixel array, there is typically a less sensitive pixel (i.e. one receiving light in the blue spectrum) and a more sensitive pixel (i.e. one receiving light in the red spectrum). A microlens is placed in physical proximity to the less sensitive pixel in order to decrease the inherent difference in sensitivity between the less sensitive pixel and the more sensitive pixel, in turn increasing the intensity of radiation incident upon the detecting area of the less sensitive pixel. The detecting area may include a photogate or a photodiode for sensing radiation.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: An imaging array of active pixel sensors uses a compact three transistor CMOS implementation for each pixel. A current source at the top of each column creates a distributed feedback amplifier for each pixel in a selected row. The reset amplifier acts as a variable resistance in the source-follower amplifier feedback circuit. The variable resistance is controlled by a range reset voltage applied to the reset amplifier thereby nulling the photodiode reset noise.

Abstract: The invention dynamically compensates for differences in data rates. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame. In another embodiment, a high frequency clock in the system is used to stall the codec for one clock. In both ways, distortion due to differences in data rates is reduced.

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N<2n−1. Each of the plurality of comparators in the converter has an input for an enabling signal, which enabling signal can be manipulated to enable or disable individual comparators and to modify their outputs. A method for converting an analog input signal into a digital signal using such a converter.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A method and device are provided that allow computation of multiple modulus conversion (MMC) outputs using little or no division operations. Instead of division operations, multiplication and logical shift operations are used to produce pseudo-quotients and pseudo-remainders, which may be corrected in a final step to produce correct MMC outputs. This allows for more efficient implementation, since division is typically less efficient than multiplication and logical shift. The method and device operate on MMC inputs that may be partitioned into sub-quotients of varying numbers of digits in any numbering system. The multiplication and logical shift operations are performed on each of the sub-quotients according to a procedure derived from long-division techniques.

Abstract: The present invention provides a method and system for switching between browser and video modes in a standalone VCD-ROM system including a VCD player and a VCD-ROM disk. A browser program is first executed in the VCD-ROM system. The browser program allows a user to navigate through the content of the VCD-ROM disk by selecting hypertext links. The hypertext links are selected by clicking on clickable text, buttons, and graphics. The system also allows the user to play a video by selecting an associated hypertext link. When the video is selected, the method of the present invention saves the return address and the address of the video. The video is then played on the video system. When the video is finished playing, the method of the present invention reloads the return address into the system. This returns the system to the original browser mode of the browser.

Abstract: A spectral shaping PCM modem communication system uses a symbol encoder to encode a data bit stream into a PCM symbol stream. A plurality of different frames are formed from the PCM symbol stream. Performance metrics are computed for each possible frame and its inversion so a decision can be made in order to select a most desirable frame and inversion Delays are injected in the data flow to allow a look-ahead and thus provide for better frame selection and inversion decisions. A channel multiplexer combines decision bits and output frames to form encoded output frames that are fed to a digital channel connected to a telephone network wherein they are converted to analog signal. A corresponding decoder converts analog signals from the telephone network to digital signals. A timing recovery and equalization means corrects sample timing and removes inter-symbol interference effects introduced by telephone networks.

Abstract: The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ.

Abstract: A spectral shaping PCM modem communication system uses a symbol encoder to encode a data bit stream into a PCM symbol stream. A plurality of different frames are formed from the PCM symbol stream. Performance metrics are computed for each possible frame and its inversion so a decision can be made in order to select a most desirable frame and inversion. Delays are injected in the data flow to allow a look-ahead and thus provide for better frame selection and inversion decisions. A channel multiplexer combines decision bits and output frames to form encoded output frames that are fed to a digital channel connected to a telephone network wherein they are converted to analog signal. A corresponding decoder converts analog signals from the telephone network to digital signals. A timing recovery and equalization means corrects sample timing and removes inter-symbol interference effects introduced by telephone networks.

Abstract: A method and apparatus for performing voltage-mode sample and hold functions while avoiding nonlinear charge injection. The method comprises oversampling an input signal and sampling an error signal, not the input signal directly, and through signal processing causing the error signal to be reduced to low amplitude. First order and higher order voltage-mode sample and hold circuitry embodiments are provided.