Abstract: A device for use in a modem configuration that enables the transfer of data from a host signal processor (HSP) to an A/D-D/A converter or CODEC with less data loss, with low noise and that can send data at varying carrier frequencies without changing the size of the buffers. The device further allows for data transfer that is flexible with any given modulation scheme, carrier frequency or baud frequency to conform with the V.34, V90, as well as prior and subsequent recommendations. The device further includes a counter for counting the number of data samples transferred between the CODEC and the HSP and for alerting the HSP to avoid an overflow condition. The counter is further configured to count beyond the physical size of the buffer in order to simplify operation in an overflow condition. A transmit buffer is included for transferring data from the HSP to the CODEC.

Abstract: An apparatus and method is provided for reducing the area of integrated circuits using cells with multiple unrelated gates. A netlist is generated which includes cells and interconnecting nets. Each cell represents a circuit and each net represents an interconnection between cells. Combinable cells of the netlist are paired to create a list. A combinable cell represents a circuit having at least one transistor formed on a substrate area. This transistor includes a diffusion layer directly coupled to a voltage source via a diffusion contact, wherein the diffusion contact is positioned adjacent an outer edge of the substrate area. A combinability score is calculated for each pair of combinable cells of the list. Each combinability score is calculated as a function of the number of nets representing direct or indirect interconnections between a pair of combinable cells. The pair of combinable cells corresponding to the highest combinability score is removed from the netlist. Thereafter, a combined cell is added.

Abstract: Techniques for applying a periodic signal to an interpolated digital signal at the input of a delta-sigma modulator to reduce noise tones a DC noise level in the output of a delta-sigma DAC. The duty cycle of the periodic signal can be adjusted to substantially cancel the DC noise level. In one embodiment, the DC noise level is first determined by, e.g., a calibration process. Then, the duty cycle of the periodic signal is adjusted according to the determined DC noise level.

Abstract: The invention dynamically compensates for differences in data rates for multistreamed systems. Any or all of the streams in a multistreamed system may be individually compensated at one time. In one embodiment, the status of an input buffer is monitored and used to change the number of oversamples within a frame of one of the number of streams. In another embodiment, a high frequency clock in the system is used to stall one of the streams for one or more clock cycles. In both ways, distortion due to differences in data rates is reduced.

Abstract: Two banks of differently-connected resistors are connected as an input to an op-amp feedback circuit.

Abstract: A decimation filtering circuit for performing a decimation operation with a decimation factor of M in a pipelined structure. A finite impulse response ("FIR") filtering of N taps for achieving a desired frequency response is designed to have an integral ratio of N/M. A total of N/M processing stages is connected in series to accumulate filtered data based on data samples of an input signal and predetermined FIR coefficients. Each of the N/M processing stages produces an accumulated output in every other M accumulations for M input data samples.

Abstract: An apparatus for compressing a speech signal into a compressed speech signal that is represented by a plurality of parameters. A time-varying digital filter is used to model the vocal tract. A number of LPC coefficients specify the transfer function of the filter updated on frame basis. An excitation signal is input to the filter analyzed on sub frame basis. This excitation signal includes either an adaptive vector quantiser code or a first pulse sequence, followed by a second pulse sequence. Selection logic is used to determine whether the adaptive vector quantiser code or the first pulse sequence better represents the speech signal. Based thereon, a switch selects either the adaptive vector quantiser code or the first pulse sequence. Thus, the parameters which are transmitted through a channel to a destination decoder include the LPC filter coefficients, either the adaptive vector quantiser code or the first pulse sequence, the second pulse sequence, and one bit indicating the state of the switch.

Abstract: A four-operator sound synthesis integrated circuit comprises a first through a fourth sound synthesis operator, a first programmable multiplier connecting the output of the first operator to the input of the second operator, a second programmable multiplier connecting the output of the second operator to the input of the third operator, a third programmable multiplier connecting the output of the third operator to the input of the fourth operator, a fourth programmable multiplier connecting the output of the first operator a first input of a four-input adder, a fifth programmable multiplier connecting the output of the second operator a second input of the four-input adder, a sixth programmable multiplier connecting the output of the third operator a third input of the four-input adder, and a seventh programmable multiplier connecting the output of the fourth operator a fourth input of the four-input adder. The product of the combination is taken from the output of the four-input adder.

Abstract: A tone generator clears all registers in a twenty-nine stage device so that the previous results are not used in the calculations for a next tone sample. A series approximation of a desired complex sound waveform is achieved by calculating the contributions of twenty-nine time steps back in time. Twenty-nine different address phases are respectively applied to twenty-nine stacked arithmetic units. Each arithmetic unit comprises a first adder that inputs the output of a previous arithmetic unit and the input of the previous arithmetic unit. A second adder inputs the result from the first adder and one of the twenty-nine address phases. The second adder then reads a waveform generator connected to a multiplier that is controlled by a common multiplication factor "B". The output of the twenty-ninth unit produces the desired tone without any of the stacked units feeding back any signals.

Abstract: A talking analog clock comprises an analog mechanical clock movement in which the minutes mechanism has attached to it a switch that opens and closes for each minute elapsed. A digital synchronizing circuit is included that senses the closing and opening of the switch and uses these events to increment a digital time-keeping circuit. A directional switch attached to a winding stem and connected to the digital synchronizing circuit allows the digital time-keeping circuit to be incremented or decremented with the winding stem. The time in the current time memory is thereafter locked in synchronization with the analog time shown on the display dial. A user can therefore set the time or an alarm time in a simple way.