Abstract: A trench power semiconductor device includes a substrate, an epitaxial layer, a drain, a first active device, a second active device, and isolation trench structures. The epitaxial layer and the drain are disposed on two surfaces of the substrate, respectively. The first active device is disposed in a first portion of the epitaxial layer and has a first source and a first gate. The second active device is disposed in a second portion of the epitaxial layer and has a second source and a second gate. The isolation trench structures are disposed between the first portion and the second portion of the epitaxial layer to electrically isolate the first active device and the second active device. Each of the isolation trench structures includes a polysilicon structure with a floating potential and an insulating layer. The insulating layer is between the polysilicon structure and the epitaxial layer.

Abstract: A split gate trench device, including a substrate, an epitaxial layer having a trench, and a split gate structure, is provided. The epitaxial layer is formed on the substrate, and the split gate structure is disposed in the trench. The split gate structure includes a shielding gate, two top gates, a shielding oxide layer, a gate oxide layer, and an inter-gate oxide layer. Each of the two top gates has a shape that is wide at the top and narrow at the bottom.

Abstract: A manufacturing method of a split gate trench device includes forming an epitaxial layer on a substrate, and forming a trench in the epitaxial layer, wherein the trench is divided into a first part and a second part above the first part. A shielding gate and a shielding oxide layer are then formed in the first part, wherein the shielding oxide layer is located between the shielding gate and the trench and exposes the second part. The second part is filled with an oxide, two grooves having a contour that is wide at the top and narrow at the bottom are then formed in the oxide, and a part of a sidewall of the trench is exposed. A gate oxide layer is formed on an exposed surface of the sidewall, and a first top gate and a second top gate are then formed in each of the two grooves.

Abstract: A gallium nitride high electron mobility transistor including a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a gate electrode, a source electrode, at least one first p-type gallium nitride island, a drain electrode, and a dielectric layer is provided. A second side of the gate electrode is opposite to a first side of the gate electrode. The first p-type gallium nitride island is disposed on the barrier layer on the second side of the gate electrode, and the drain electrode is also disposed on the barrier layer on the second side of the gate electrode and covers the first p-type gallium nitride island. The dielectric layer is disposed between the drain electrode and the first p-type gallium nitride island, so that the first p-type gallium nitride island is electrically floating.

Abstract: A trench power semiconductor device includes a substrate, an epitaxial layer, a drain, a first active device, a second active device, and isolation trench structures. The epitaxial layer and the drain are disposed on two surfaces of the substrate, respectively. The first active device is disposed in a first portion of the epitaxial layer and has a first source and a first gate. The second active device is disposed in a second portion of the epitaxial layer and has a second source and a second gate. The isolation trench structures are disposed between the first portion and the second portion of the epitaxial layer to electrically isolate the first active device and the second active device. Each of the isolation trench structures includes a polysilicon structure with a floating potential and an insulating layer. The insulating layer is between the polysilicon structure and the epitaxial layer.

Abstract: A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.

Abstract: A gallium nitride high electron mobility transistor including a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a gate electrode, a source electrode, a drain electrode, and multiple first p-type gallium nitride islands is provided. A second side of the gate electrode is opposite to a first side of the gate electrode. The first p-type gallium nitride islands are respectively disposed between a first side of the drain electrode and the second side of the gate electrode, and the first p-type gallium nitride islands are electrically floating.

Abstract: A control device of a power switch includes a voltage boost circuit, a discharge circuit and a bias voltage generating circuit. The voltage boost circuit generates a control voltage at a control end of the power switch by boosting a base voltage. The discharge circuit provides a discharge path between the control end of the power switch and a reference ground end according to a bias voltage. The bias voltage generating circuit compares an output voltage on an output end of the power switch with the control voltage to generate a comparison result, and generates the bias voltage according to the comparison result.

Abstract: A manufacturing method of a trench MOSFET includes forming a trench gate in an epitaxial layer having a first conductivity type on a substrate, performing implantations of a dopant having a second conductivity type on the epitaxial layer in which an implantation dose is gradually reduced toward the substrate, performing a first drive-in step to diffuse the dopant having the second conductivity type in an upper half of the epitaxial layer to form a body region, implanting a dopant having the first conductivity type on a surface of the epitaxial layer, performing a second drive-in step to diffuse the dopant having the first conductivity type to form a source region, comprehensively implanting the dopant having the second conductivity type at an interface of the body region and the source region to form an anti-punch through region having a doping concentration higher than that of the body region.

Abstract: A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.

Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.

Abstract: A voltage converting circuit and a control circuit thereof are provided. The control circuit includes a comparator, a clock generator, and a boost circuit. The comparator compares an input voltage with an output voltage to generate a comparison signal. The clock generator generates a clock signal according to the comparison signal to enable the clock signal to have a first frequency in a first time interval and to have a second frequency in a second time interval. The first frequency is higher than the second frequency. The first time interval occurs before the second time interval. The boost circuit receives the clock signal, pulls up a control signal of a driving switch in the first time interval according to a first driving capability, and generates the control signal in the second time interval according to a second driving capability. The first driving capability is greater than the second driving capability.

Abstract: A power circuit including a switching circuit and a soft start control circuit is provided. A first terminal of the switching circuit is configured to receive an input voltage. A control terminal of the switching circuit receives a control signal. A second terminal of the switching circuit is configured to provide an output voltage. The soft start control circuit generates the control signal according to the output voltage and a first reference voltage to control a turn-on state of the switching circuit. The soft start control circuit switches a slope of the control signal from a first slope to a second slope after the switching circuit is turned on and when a voltage value of the control signal is equal to a second reference voltage, wherein the first slope is less than the second slope to reduce an inrush current at the time when the switching circuit is turned on.

Abstract: A control circuit of a load switch including a charge pump circuit, an oscillator, and a current signal generator is provided. The charge pump circuit generates a control signal according to a clock signal. The load switch is turned on or turned off according to the control signal. The oscillator generates the clock signal according to a control current. The current signal generator provides a resistor string to receive a power voltage. The resistor string of the current signal generator generates a sensed current or a sensed voltage according to the power voltage. The current signal generator generates the control current according to a reciprocal of the sensed current or a square of the sensed voltage. A frequency of the clock signal is negatively related to the power voltage.

Abstract: A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage.

Abstract: A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage.

Abstract: A method of manufacturing a gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes orderly forming a channel layer, a barrier layer, a doped GaN layer, an undoped GaN layer, and an insulating layer on a substrate, and then removing a portion of the insulating layer to form a trench. A gate metal layer is formed on the substrate to cover the insulating layer and the trench, and then a mask layer aligned with the trench is formed on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped GaN layer and the doped GaN layer are removed, and then the mask layer is removed.

Abstract: A power switch circuit including first and second transistors, and a control circuit is provided. A first end of the first transistor serves as an input terminal of the power switch circuit. A second end of the first transistor is coupled to a node. A control end of the first transistor receives a first control voltage. A first end of the second transistor serves as an output terminal of the power switch circuit. A second end of the second transistor is coupled to the node. A control end of the second transistor receives a second control voltage. The control circuit detects a voltage of the node to determine a type of series connection between the first and second transistors, and generates the first and second control voltages to control a turned-on state of another of the first and second transistors after turning on one of the first and second transistors.

Abstract: A voltage converting circuit and a control circuit thereof are provided. The control circuit includes a comparator, a clock generator, and a boost circuit. The comparator compares an input voltage with an output voltage to generate a comparison signal. The clock generator generates a clock signal according to the comparison signal to enable the clock signal to have a first frequency in a first time interval and to have a second frequency in a second time interval. The first frequency is higher than the second frequency. The first time interval occurs before the second time interval. The boost circuit receives the clock signal, pulls up a control signal of a driving switch in the first time interval according to a first driving capability, and generates the control signal in the second time interval according to a second driving capability. The first driving capability is greater than the second driving capability.

Abstract: A voltage converting apparatus includes a first comparator, a second comparator, a constant on-time signal generator, a driving stage circuit, an inductor and a reference signal generator. The first comparator compares a feedback signal and a first reference signal to generate a first comparison result. The second comparator compares the first comparison result with a second reference signal to generate a second comparison result. The constant on-time signal generator generates a constant on-time signal. The reference signal generator generates the second reference signal with reducing voltage during a first time period according to an input voltage or a driving signal, and generates the second reference signal with rising voltage during a second time period according to a preset slope. The reference signal generator sets the first time period and the second time period according to the constant on-time signal.