Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: A thick glass passivation layer comprises an alternating sequence of structurally dissimilar but chemically compatible layers of material over the surface of a substrate, so as to provide sufficient elasticity to compensate for thermal expansion differences that would otherwise crack causing in thick monolithic films. A first layer comprises glass that has been deposited over the surface of the structure using chemical vapor deposition. A second layer of the passivating glass material is then provided on the substrate using a spinning technique. The chemical vapor deposition and spun layers continue to be applied in an alternating fashion until a film having the desired thickness is formed. Each chemical vapor deposition layer provides an elastic cushion for the subsequently spun layers. The spun layers allows a planar topography to be maintained without the need for high temperatures.

Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in a required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

Abstract: A method and means for reducing signal propagation losses in very large scale integrated circuits is provided comprising a ground plane located adjacent to, but insulated from, a conductive signal layer overlying an active region in a semiconductor substrate. While, the ground plane is preferrably disposed between the signal layer and the substrate, it may be disposed above the signal layer. Moreover, two or more signal layers may be employed and sandwiched between a pair of ground planes.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: The present invention is an improved subscriber line interface circuit which allows fast detection of an off-hook signal in the presence of a ringing signal during an answer mode while also permitting fast detection of dialing pulses during a calling mode. A programmable filter is used in the supervision circuit of the SLIC to allow the cutoff frequency of the filter to be varied so that the 20 Hz ringing signal will be attenuated during a ringing sequence and dialing pulse rates up to 20 Hz will be passed by the filter during the calling mode. A clamping amplifier is used to clamp the received signal to a maximum of 1.5 times the loop threshold current. This eliminates the large variations in the rise and fall times of the pulse dialing signal due to variations in the loop current caused by varying impedances of the telephone line. The filter is programmed by using an analog switch to bypass certain filter elements.

Abstract: A method and apparatus for testing an electrical device and/or circuit in which the device or circuit is stimulated with a known input signal and in which three or more measurements of the response of the device or circuit to such stimulus are taken and utilized to predict a final value of such response according to a predetermined relationship between such predicted final response and the measured response values. Typically the present invention can predict such final value without waiting for the actual final value of the response to occur.

Abstract: A monochrome or color imager having interlaced, non-interlaced or pseudo-interlaced readout utilizing pixels arranged in groups forming equilateral triangles which are interleaved. Separate vertical shift registers driven by different clock signals to implement different forms of interlaced, non-interlaced and pseudo interlaced signal readout are located on each side of the rectangular array and are coupled to alternating row address lines and different groups of column lines in the array. The clock signals driving each shift register can be controlled to select monochrome or color operation in one of the above noted modes of readout. A horizontal shift register is connected to the gates of MOS coupling transistors which couple the column or bit lines of the array to a pair of monochrome outputs, while a second shift register is connected to the gates of MOS coupling transistors which couple the column or bit lines of the array to a trio of color outputs for color output signals.

Abstract: There is disclosed herein a stress relieved intermediate insulating layer consisting of one or more layers of spun-on glass lying over a metalization pattern. The spun-on layers are allowed to crack from thermal stress imposed upon the structure. The cracks in the spun-on layers are then filled with a glass layer deposited by CVD or LPCVD.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: An improved integrated injection logic structure utilizes a current mirror in conjunction with each switching transistor (M.sub.1, M.sub.2) of the integrated injection logic circuit of this invention by connecting one of a plurality of collectors (O.sub.0, P.sub.0) of the switching transistor to the base of said switching transistor. In this manner, the current flowing through conducting switching transistors is limited by the current mirror. This limited current flow through conducting switching transistors, as well as the use of voltage pull up means (D.sub.1, D.sub.2) connected to the collectors of the switching transistors prevents the saturation of conducting switching transistors.

Abstract: An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV.sub.

Abstract: A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.

Abstract: A method for forming a substantially planar inorganic dielectric layer over a predetermined pattern of electrical interconnects comprises the steps of reacting phosphoric acid and a trivalent metallic halide compound with an aliphatic solvent to form a coating fluid. The coating fluid is then spun onto the semiconductor device to form a layer over the electrical interconnect. The resultant device is then baked at a first temperature to drive off the solvent and then baked at a second, higher temperature, in order to promote the glass forming reaction. This process is repeated as required to form a coating layer having a thickness which exhibits levelling characteristics of such high quality that fine topography can be carried out on succeeding layers of metal in order to form additional interconnect layers with precision.

Abstract: Three sets of pincer units depend from a flat palm, each pincer unit having a pinching gap at its distal end for engaging a loaded circuit board by its edges and holding it in a spaced-apart relationship with the palm. Each pincer unit includes a finger having a flange at its distal end and a thumb slideably mounted on the finger so as to define a variable pinching gap. The fingers are mounted for prehensiling movement away from one another for bracketing a board to be picked up and toward one another so that the board to be picked up may be squeezed between them.The invention includes a method for picking up a loaded circuit board which involves bracketing a board to be picked up between a set of pincer units, squeezing the board by moving the pincer units toward one another against opposing edges of the board while simultaneously pinching each edge engaged with the pincer units.

Abstract: The present invention relates to a method and apparatus for forming a ball bond between a fine wire such as aluminum wire and a surface with the ball bond being approximately radially symmetric about a principal axis of a portion of the wire. The apparatus may include a plurality of electrodes radially spaced about the wire to define gaps between each electrode and the tip of the wire and a plurality of resistance elements. A voltage source may be connected to form a circuit consisting of plural electrically parallel legs, each of which includes the series combination of a resistance element, an electrode and an arc path between the electrode and the tip of the wire. A molten ball is formed at the end of the wire when arcs are essentially simultaneously produced between the electrodes and the tip of the wire. In a preferred embodiment, the resistances of the resistance elements are approximately equal.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: An argon-fluorine (ArF) excimer laser is used to selectively heat various Si.sub.3 N.sub.4 materials used in the manufacture of semiconductor devices to elevated temperatures while maintaining active device regions and electrical interconnects at relatively low temperatures, to, for example, anneal the structural layer, induce compositional changes or densification and/or flow of the silicon nitride-based material to round off sharp edges and stops, all without damaging or appreciably affecting the active regions and electrical interconnects of a semiconductor device.