Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in a required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

Abstract: A method and means for reducing signal propagation losses in very large scale integrated circuits is provided comprising a ground plane located adjacent to, but insulated from, a conductive signal layer overlying an active region in a semiconductor substrate. While, the ground plane is preferrably disposed between the signal layer and the substrate, it may be disposed above the signal layer. Moreover, two or more signal layers may be employed and sandwiched between a pair of ground planes.

Abstract: The present invention is an improved subscriber line interface circuit which allows fast detection of an off-hook signal in the presence of a ringing signal during an answer mode while also permitting fast detection of dialing pulses during a calling mode. A programmable filter is used in the supervision circuit of the SLIC to allow the cutoff frequency of the filter to be varied so that the 20 Hz ringing signal will be attenuated during a ringing sequence and dialing pulse rates up to 20 Hz will be passed by the filter during the calling mode. A clamping amplifier is used to clamp the received signal to a maximum of 1.5 times the loop threshold current. This eliminates the large variations in the rise and fall times of the pulse dialing signal due to variations in the loop current caused by varying impedances of the telephone line. The filter is programmed by using an analog switch to bypass certain filter elements.

Abstract: A method and apparatus for testing an electrical device and/or circuit in which the device or circuit is stimulated with a known input signal and in which three or more measurements of the response of the device or circuit to such stimulus are taken and utilized to predict a final value of such response according to a predetermined relationship between such predicted final response and the measured response values. Typically the present invention can predict such final value without waiting for the actual final value of the response to occur.

Abstract: There is disclosed herein a stress relieved intermediate insulating layer consisting of one or more layers of spun-on glass lying over a metalization pattern. The spun-on layers are allowed to crack from thermal stress imposed upon the structure. The cracks in the spun-on layers are then filled with a glass layer deposited by CVD or LPCVD.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to the collector of the vertical NPN through a buried contact region accessed through a sink region formed in an adjacent island of semiconductor material. A field implantation beneath the isolation oxide avoids implanting impurity along the sidewalls of the semiconductor material adjacent the field oxidation and therefore provides both vertical and lateral isolation from one silicon island to another. Substantial reductions in sink sizes and cell sizes are obtained by elminating the field diffusions from the sidewalls of the semiconductor islands. The lateral PNP transistor serves as an active load for a memory circuit constructed using the structure of this invention. The process also can be used to manufacutre PROMS from vertical NPN transistors. An LV.sub.

Abstract: A method for forming a substantially planar inorganic dielectric layer over a predetermined pattern of electrical interconnects comprises the steps of reacting phosphoric acid and a trivalent metallic halide compound with an aliphatic solvent to form a coating fluid. The coating fluid is then spun onto the semiconductor device to form a layer over the electrical interconnect. The resultant device is then baked at a first temperature to drive off the solvent and then baked at a second, higher temperature, in order to promote the glass forming reaction. This process is repeated as required to form a coating layer having a thickness which exhibits levelling characteristics of such high quality that fine topography can be carried out on succeeding layers of metal in order to form additional interconnect layers with precision.

Abstract: A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.

Abstract: The present invention relates to a method and apparatus for forming a ball bond between a fine wire such as aluminum wire and a surface with the ball bond being approximately radially symmetric about a principal axis of a portion of the wire. The apparatus may include a plurality of electrodes radially spaced about the wire to define gaps between each electrode and the tip of the wire and a plurality of resistance elements. A voltage source may be connected to form a circuit consisting of plural electrically parallel legs, each of which includes the series combination of a resistance element, an electrode and an arc path between the electrode and the tip of the wire. A molten ball is formed at the end of the wire when arcs are essentially simultaneously produced between the electrodes and the tip of the wire. In a preferred embodiment, the resistances of the resistance elements are approximately equal.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: An argon-fluorine (ArF) excimer laser is used to selectively heat various Si.sub.3 N.sub.4 materials used in the manufacture of semiconductor devices to elevated temperatures while maintaining active device regions and electrical interconnects at relatively low temperatures, to, for example, anneal the structural layer, induce compositional changes or densification and/or flow of the silicon nitride-based material to round off sharp edges and stops, all without damaging or appreciably affecting the active regions and electrical interconnects of a semiconductor device.

Abstract: A novel zero insertion (and removal) force multi-pin coaxial connector for providing connections via controlled impedance paths is formed using a conductive elastomer as a frame (8) which forms the shield of a plurality of coaxial connectors and a plurality of circular openings formed in the conductive elastomer frame, each said opening corresponding to a single coaxial connection. An annular insulating ring (5), which forms the dielectric of an associated one of the coaxial connectors, is located in each annular opening of the conductive elastomer frame and an elastomer through-conductive member (6) which forms the center conductor of its associated coaxial connector is located within the circular opening of each insulating ring. In this manner, the conductive elastomer frame forms the shield of a plurality of coaxial connectors.

Abstract: A method and system for loading test data into individual pin memories of an automatic digital test system, particularly of the in-circuit type. Test data in the form of test vectors are accessed from a test vector store simultaneously with the access of a digital test pin selection signal. The test pin selection signal accessed with the test data is then used to selectively load the test data into a pin memory identified by the pin selection signal, thereby permitting the loading of test data into any one of a group of individual pin memories. In the preferrred embodiment the test data, a test vector, is stored in a test vector store in association with a test pin selection signal. When the test vector is read from memory, the test pin selection signal is also read by the same address signal.

Abstract: A data channel for a digital tester includes a random access local memory containing a main vector sequence, a subroutine vector sequence, and a test vector list. An index register is loaded with the address of the first vector in the list of vectors that is to be inserted as a variable into a vector stream. A sequence instruction selects the index register as the source of a test vector address when a variable vector is to be inserted into the vector stream at a point in a subroutine. The sequence instruction also resets the index register to a state which determines the address of the next variable to be inserted into the test vector pattern.

Abstract: An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

Abstract: A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

Abstract: A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .