Abstract: A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. When the data is retrieved from memory similar error logic generates a second error code. The first and second error codes are compared, and if the codes are identical the data is assumed to be correct. If codes differ then the data is discarded or errors therein are identified and corrected.

Abstract: MOS Control circuitry for incorporation on a microcomputer IC chip for assuring adequate power to maintain the data in an associated static random access memory. A rechargeable battery provides standby power, and the voltage level of the battery is compared with the microcomputer V.sub.cc supply. Whenever V.sub.cc drops below a predetermined level, such as the standby battery voltage level, the circuitry disconnects the V.sub.cc from the memory input power and replaces it with standby battery power. When V.sub.cc is returned to the system, a gate applies a trickle charge to the battery.

Abstract: A technique is disclosed for protecting integrated circuits from alpha particles. A central portion of a radiation resistant insulating substrate upon which electrically conductive leads are disposed is positioned in proximity to the integrated circuit. When the leads are electrically connected to the integrated circuit, the central portion of the substrate is allowed to remain over the integrated circuit to protect the integrated circuit. The insulating substrate typically comprises a polyimide film resistant to alpha particles.

Abstract: A method for fabricating insulating regions in an integrated circuit structure is disclosed in which the insulating regions do not encroach upon the surrounding integrated circuit and in which a substantially planar surface across the top of the insulating material and the substrate is created. The method includes the steps of removing portions of the substrate wherever the insulating regions are to be formed, beginning to deposit insulating material across the substrate and in the openings created, and, while continuing to deposit insulating material simultaneously removing insulating material from generally horizontal surfaces and redepositing it on generally vertical surfaces of the substrate and the openings until a planar surface results.

Abstract: A temperature-compensated reference voltage circuit includes a transistor having a positive temperature coefficient of current. A circuit for establishing a predetermined current in the positive-temperature-coefficient-of-current transistor is connected to that transistor. A predetermined resistance serially connects the positive-temperature-coefficient-of-current transistor with a transistor having negative temperature coefficient of base-to-emitter voltage. The temperature-compensated reference voltage is established between the transistors. The temperature-compensated reference voltage circuit is particularly useful in a supply voltage sense amplifier circuit for thermal printhead drive transistors or other load elements. The sense amplifier circuit includes a circuit for comparing the reference voltage and a supply voltage. An output is adapted to be connected to a load for receiving the supply voltage.

Abstract: A method and circuitry are disclosed for correcting bit errors introduced by random events in a data recirculating memory, such as a charge coupled memory device or a bubble memory. The bit errors, caused by random events such as by alpha particle bombardment or other causes, are corrected in circuitry that generates row and column parity bits corresponding to various segments of the information stored in the memory. Changes in the row and column parity bits uniquely define the location of failed bits circulating through the memory even though each failed bit has no fixed address, so that error detection circuitry thereafter may correct the error during the next or a subsequent bit recirculating cycle. The invention facilitates the use of very large memories, for example, on the order of one billion bits or more.

Abstract: A low temperature LPCVD process for co-depositing metal and silicon to form metal silicide on a surface such as the surface of a semiconductor integrated circuit wherein the metal is selected from the group consisting of tungsten, molybdenum, tantalum and niobium. A reactor which contains the surface is maintained at a temperature of about 500.degree.-700.degree. C. The reactor is purged by the successive steps of introducing an inert gas into the reactor, introducing a reducing atmosphere into the reactor and introducing hydrogen chloride gas into the reactor. Silane is then introduced into the reactor such that a base layer of polysilicon is formed on the surface. Then, while maintaining silane introduction to the reactor, metal chloride vapor is simultaneously introduced into the reactor such that metal and silicon are co-deposited on the polysilicon as metal silicide.

Abstract: A video game apparatus for connection to a standard television set and including an electronics-containing console having a plurality of parameter selection buttons and a chute mechanism for receiving a replaceable cartridge-containing supplementary electronic circuitry, and a pair of hand controllers for providing player control inputs to the console electronics. Improved connector apparatus is associated with the chute mechanism to enable electrical connection to be made to a cartridge contained printed circuit board with a minimum of insertion force.

Abstract: An alignment target for an electron-beam direct write system is formed on a wafer of semiconductor material. First, a layer of silicon oxide is formed on a surface of the wafer. Then a layer of silicon nitride is formed on the oxide. Next, an opening is etched in the nitride layer to expose a surface portion of the oxide. The surface portion of the oxide is then etched to form a hole in the oxide. The hole is formed such that the oxide layer is undercut beneath the nitride layer such that a cantilevered nitride overhang is formed around the perimeter of the hole. A layer of aluminum is then deposited over the nitride layer.

Abstract: A universe of probes is contained within a platen in a spaced-apart, substantially parallel relationship with one another with their tips pointing in the same direction. Each probe is free to move longitudinally between an advanced or test position and a retracted position. The platen nests into a wired personalizer having probe selector posts upstanding therein in a pattern corresponding to the pattern of test points on a circuit board to be tested. These posts serve to push up or advance the probes needed to test a particular type of circuit board. The posts are conductive and each is individually connected to the test system. The circuit board to be tested rests on a special deformable gasket so that its test points are suspended over and aligned with the advanced test probes. When the fixture is evacuated, the circuit board to be tested is drawn downwardly so that the test points on the board make electrical contact with the tips of the advanced probes.

Abstract: Bromine-containing plasma is utilized to inhibit corrosion of aluminum or aluminum alloy films which have been etched utilizing a chlorinated plasma.

Abstract: Semiconductor memory devices are tested by using a special purpose computer which uses simple test patterns to determine the weakest bits of the device and then tests only these relatively few "weak bits" and structurally and operationally adjacent bits using highly complex test patterns to determine if the device is functioning properly. This procedure considerably reduces testing time over that required using prior art techniques.

Abstract: A method for statistically calibrating a digital-to-analog converter with an electronic test system. The digital-to-analog converter is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analogconverter is detected by an analog-to-digital converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the digital-to-analog converter under test.

Abstract: A data latch of the kind having at least two operative modes, a transmitting or transparent mode or condition for transmitting data signals through the latch, and a latching mode or condition for latching and temporary storage by feedback of data signals in the latch. According to the invention there is provided in the data latch a pregate for pregating feedback signals in the latch. The pregate is adapted and coupled to provide positive feedback data signals for reinforcing previously entered data in the latching mode, and gating signals for passing input data in the transmitting mode.

Abstract: A diffused resistor included in a Schottky device formed in a planar semiconductor material comprises a resistor diffusion formed in the surface of the material and a contact diffusion formed in the surface of the material, the configuration of the contact diffusion being essentially coincident with the shape of the resistor at the location at which ohmic contact to the resistor diffusion is made.

Abstract: An electronic circuit for simultaneously erasing all the information stored in an electronic information storage device and entering a predetermined new pattern of information into the storage device comprises a plurality of bistable semiconductor cells with an additional transistor current-conducting region included on a predetermined side of each cell. The additional current-conducting regions in the cells along each word row are coupled to an additional word line which connects to a current switch for the row. At an appropriate pulse signal, the current switch activates to switch row current temporarily from the standard current-source word line, which conducts holding current to the row during normal operation, to the additional word line, thereby erasing the old data and entering the new information bits.

Abstract: A method for preventing the post-etch corrosion of aluminum or aluminum alloy film which has been etched utilizing chlorinated plasma wherein the etched film is exposed to fluorinated plasma.

Abstract: An electronic advance and ignition control system incorporating the advance utilizes a fixed advance threshold compared with amplitude of an RPM sensitive input waveform from a distributor in combination with a timing circuit, which establishes a predetermined RPM rate above which the advance operates. The electronic advance accurately duplicates the function of conventional centrifugal and vacuum and advance retard mechanisms in controlling timing of an ignition coil drive signal. The electronic advance is provided as part of an ignition control integrated circuit which can operate in a stand alone mode or share control of the ignition system with a microprocessor through interface circuits also forming part of the integrated circuit.

Abstract: An integrated injection logic device is formed in a pocket of semiconductor material surrounded by oxide isolation, and separated from a substrate by an intervening region of opposite conductivity. The steps for forming the integrated injection logic device include depositing a first material which includes a first conductivity type impurity over a first portion of the epitaxial layer, treating the first material to cause at least some of the first conductivity type impurity to enter the epitaxial layer, and introducing an opposite conductivity type impurity into a second portion of the epitaxial layer. Typically, the first material is polycrystalline silicon doped with p conductivity type impurity.

Abstract: High-speed testing circuitry which, when coupled to one terminal of a multi-terminal electronic device, such as an integrated circuit, can either supply test stimuli signals up to a frequency of 30 MHz, receive output signals produced by the device under test in response to test stimuli signals applied by associated test circuits and compare these signals against computer predicted signals, or provide for parametric testing of the device. .Iadd.