Abstract: A novel process is disclosed for the selective etching of a protective layer over a substrate according to a predetermined pattern, which does not involve the use of chemical vapor deposition or vacuum techniques. The process incorporates the techniques of electroless metal deposition after first applying a mask which is positive with respect to the predetermined pattern. In alternative embodiments, the application to the masked protective layer of an agent catalytic to the reception of electroless metal deposition is followed by either immersion in an electroless plating bath and subsequent mask removal, or by mask removal and subsequent immersion in the electroless plating bath. In either embodiment, the protective layer is effectively masked and patterned for plasma etching. The process is useful in forming openings in the protective layer to permit selective doping of the underlying substrate.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: The method of the invention provides a thin film deposit of a binary glass for use in integrated circuits which binary glass has a softening or flow point far below temperatures at which glasses normally used in connection with integrated circuits flow. After the binary glass has been deposited (on a semiconductor substrate), it is heated and reflowed. Preferably the glass comprises a mixture of germanium dioxide and silicon dioxide wherein the germanium dioxide is no greater than approximately 50 mole percent of the mixture. Phosphorus is added to the glass film for passivation of the underlying devices.

Abstract: A method for scanning the top surface of a semiconductor wafer prevents damage to the wafer (11) by ensuring that the laser beam (13) does not cross over the edge (11a) of the wafer during the scanning process nor approach within one (1) to two (2) millimeters to the edge of the wafer.

Abstract: A method of removing bulk impurities from a semiconductor wafer is described comprising the steps of lapping the front and back surfaces of the wafer to remove 35 to 40 microns of material therefrom and to make the surfaces parallel, heating the wafer at a predetermined temperature preferably equal to or above the highest temperature to be used in subsequent device fabrication, etching the front and back surfaces of the wafer to remove 35 to 40 microns of material therefrom and thereafter polishing the front surface of the wafer for removing 20 microns of material therefrom. By means of the above process the number of surface defects caused by strain producing centers in the crystal lattice of the wafer is reduced from 500,000 defects per square centimeter to less than 1,000 defects per square centimeter.

Abstract: An address gate for a random access memory includes a pair of emitter-coupled and collector-coupled transistors, and another transistor emitter-coupled to the pair of transistors. Complimentary outputs are read at the coupled emitters of the pair of transistors and the collector of the other transistor respectively, there being an input signal applied to the base of one of the pair of transistors, and a control signal applied to the base of the other of the pair of transistors, which overrides the operation of one of the pair of transistors when the control signal is in its high state.

Abstract: Diagnostic testing of a charge coupled device is facilitated by interconnecting the reference node of the sense amplifier for each data block in the CCD device with a probe contact on the device, thereby eliminating the need for applying a microprobe to the sensitive reference node. Reference voltages under different operating conditions can be evaluated by measuring the device generated reference voltage or by applying variable reference voltages through the probe contact to the reference node.

Abstract: A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

Abstract: Apparatus for amplifying output signals from a charge coupled area imaging device includes a resettable first floating gate amplifier connected to sense charge in the charge coupled device output register at a first location, a second floating gate amplifier connected to sense charge in the charge coupled device output register at a second location, and a charge limiting well disposed between the first location and the second location to remove charge in excess of a desired amount before the output signals are sensed at the second location. The dual preamplifiers permit optimization of the output signals from the charge coupled imaging device for two substantially different light levels by providing a substantially lower noise equivalent input signal level from the second preamplifier.

Abstract: An interruptible microprogram sequencing unit (MSU) for providing a sequence of microinstruction addresses to a control memory containing microinstructions for the operation of a microprogrammed apparatus. The MSU includes an address output for providing microinstruction addresses to the control memory, an address bus connected to the address output such that a plurality of microinstruction addresses applied to the address bus are sequentially provided to the address output, means connected to the address bus for applying the plurality of microinstruction addresses to the address bus, an interrupt return register operably connected to the address bus for receiving a microinstruction address from the address bus and storing the received microinstruction address, and means connected to the address bus for interrupting the sequence of microinstruction addresses and effecting storage of a microinstruction address on the address bus in the interrupt return register.

Abstract: A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprises an arithmetic logic unit having a first and a second input and an output, a plurality of registers, at least one of which is a bidirectionally shifting register and multiplexing apparatus for selectively coupling each of said plurality of registers to said first and said second inputs and said output of said arithmetic logic unit.

Abstract: A sense amplifier for determining the binary logic state of a dynamic memory cell (11.sub.x,y) preamplifies an initial voltage difference established between a first input line (17.sub.y) coupled to the memory cell (11.sub.x,y) and a first reference line (18.sub.y) coupled to a reference cell (32.sub.y). The resulting amplifies voltage difference is generated between a second input line (19) coupled through a coupling device (Q51.sub.y) to the first input line (17.sub.y) and a second reference line (20) coupled through another coupling device (Q52.sub.y) to the first reference line (18.sub.y) by capacitively charging the second lines (19 and 20) preferably with a pair of capacitors (C61 and C62) individually coupled to the second lines (19 and 20). A differential sensing device (90) senses the amplified voltage difference to determine the logic state which is fully restored to the memory cell (11.sub.x,y).

Abstract: A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.

Abstract: In the present invention, a length of elongated single crystal ingot is mounted adjacent its ends and is ground while being rotated to provide a cylindrical shape. While still mounted, the crystal is rotated into a position to be x-rayed for the grinding of a flat thereon with the crystal in a non-rotated state.

Abstract: A transistor logic output device is provided with an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging the so-called capacitive feedback Miller current generated during the low to high potential transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The active element discharging transistor is controlled at its base by the potential at the collector of the phase splitter element and is coupled to follow changes in voltage at the phase splitter collector for receiving base drive current during the transition from low to high potential at the device output and when the phase splitter is not conducting.

Abstract: In a transistor logic output device the improvement comprising an active element discharging transistor coupled between the base of the pulldown element transistor and ground or low potential for actively controlling a route to ground or low potential for diverting and discharging so-called capacitive feedback Miller current generated during the low to high voltage transition at the output of the device resulting from base-collector junction capacitance in the pulldown element transistor. The invention includes capacitive coupling means coupled at the base of the active element discharging transistor to follow changes in voltage at the device output and capacitively feed back current during transistion from low to high potential at the device output for driving the base of the discharge transistor thereby providing a low impedance path to ground or low potential at the base of the pulldown element transistor for diverting and discharging capacitive Miller feedback current.

Abstract: A metal-semiconductor field-effect transistor is formed by providing a blanket layer of the same conductivity type as the semiconductor body, with field oxide subsequently being grown, and with a region of opposite conductivity type being formed to extend partially under the field oxide, the initial blanket layer acting as the field implant region of the field-effect transistor.

Abstract: A method for forming a shaped buried layer in a semiconductor structure includes the steps of removing a portion of semiconductor material from adjacent the surface of the semiconductor substrate to form an indentation, introducing a dopant into the surface of the indentation to form regions of impurity in the semiconductor substrate, forming a region of epitaxial material on the surface of the indentation, and forming regions of insulating material to surround the epitaxial material.

Abstract: As a cassette holding wafers in an etchant bath is rotated, nitrogen gas is bubbled through the cassette adjacent the wafers to agitate the wafers, so as to ensure that etchant reaches all edge portions of the wafers.

Abstract: In a transistor circuit a linear relationship between V.sub.BE and temperature is obtained by using high base sheet resistivity devices, such as super beta NPN transistors, or lateral PNP transistors. Alternatively, high base sheet resistivity devices are fabricated having a non-linear V.sub.BE vs. temperature relationship that is matched to the non-linear V.sub.BE vs. temperature relationship of NPN devices and/or the non-linear resistivity of diffused resistors over temperature, such that the sum or difference of the non-linear terms will exactly cancel, providing a linear voltage vs. temperature relationship for the circuit as a whole.