Abstract: This application discusses among other things, apparatus and method for transmitting data with an analog signal without significantly distorting the analog signal. In an example, an apparatus can include an audio channel, a capacitor coupled to a first conductor of the audio channel, the capacitor configured to couple an analog representation of a digital data signal with an analog audio signal on the audio channel, and a frequency modulator configured to receive the digital data signal and to modulate a frequency of an output signal of the frequency modulator based on a logic level of the digital data signal, wherein the analog representation of the digital data signal includes the frequency of the output signal of the frequency modulator.

Abstract: In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.

Abstract: In one general aspect, an apparatus can include an input terminal, an output terminal and a ground terminal. The apparatus can also include an overcurrent protection device coupled between the input terminal and the output terminal. The apparatus can further include a thermal shunt device coupled between the output terminal and the ground terminal, the thermal shunt device being configured to, at a threshold temperature, operate in a thermally-induced low-impedance state.

Abstract: One embodiment provides a start-up circuit that includes start-up switch circuitry comprising a switch coupled an input voltage rail and configured to generate a start-up voltage; wherein the start-up switch circuitry is configured to generate the start-up voltage to have a predefined voltage level within a predetermined time period. The start-up circuit also includes first controller circuitry configured to control the switch to turn ON and OFF based on, at least in part, the start-up voltage; and wherein when the switch is turned ON the start-up switch circuitry generates the start-up voltage and when the switch is turned OFF the start-up circuitry discontinues the start-up voltage.

Abstract: The present disclosure is related to alleviation of at least some of the drawbacks of the previously known implementations and to provide an improved alternative. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a planarized surface.

Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are described. The SiC BJT comprises a collector region, a base region and an emitter region disposed as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically disposed between the first portion and the emitter region in the stack.

Abstract: In one general aspect, an apparatus can include an energy storage device configured to store energy during an unclamped inductive switching test of a target device, and a switch device configured to shunt at least a portion of energy away from the target device in response to the target device changing from a breakdown state to a failure state.

Abstract: A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.

Abstract: This document refers to multi-die micromechanical system (MEMS) packages. In an example, a multi-die MEMS package can include a controller integrated circuit (IC) configured to couple to a circuit board, a MEMS IC mounted to a first side of the controller IC, a through silicon via extending through the controller IC between the first side and a second side of the controller IC, the second side opposite the first side, and wherein the MEMS IC is coupled to the through silicon via.

Abstract: In an example, a driver for a micro-electro-mechanical-system (MEMS) device can include a first input configured to receive a first command signal including an oscillatory command signal, a second input configured to receive a second command signal including a bias command signal, and an amplifier configured to receive a high voltage supply, to provide, to the MEMS device, a closed-loop output signal responsive to both the first command signal and the second command signal in a first state, and to provide an open loop output signal configured to substantially span a voltage range of the high voltage supply in a second state.

Abstract: This document discusses, among other things, methods for controlling a Rail-to-Rail enabling signal, including providing a first signal of an input signal of a control circuit to a level switching circuit, performing, by the level switching circuit, enabling control according to a high level and a low level of the first signal, and outputting, by the level switching circuit, a disabling signal in case of a failure of a power supply coupled to the level switching circuit. The document also discusses a circuit for controlling a Rail-to-Rail enabling signal and a level switching circuit configured to output a disabling signal properly to provide an accurate enabling control signal for equipment operated under control of an enabling control in case of the failure of the power supply.

Abstract: This document discusses apparatus and methods for a boost converter start-up circuit. In an example, a start-up circuit can include a linear current generator configured to couple a supply terminal of the voltage converter to an output terminal of the voltage converter. The linear current generator can include a modified current mirror and a feedback circuit configured to provide a first representative of an output voltage of the output terminal to an input of each of a first and a second adjustable current source of the modified current mirror.

Abstract: An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.

Abstract: A resonant converter system includes a first stage having inverter circuitry and resonant tank circuitry configured to generate an AC signal from a DC input signal, a transformer configured to transform the AC signal, and a second stage. The second stage features synchronous rectifier (SR) circuitry including a plurality of SR switches each having a body diode and SR control circuitry. SR control circuitry is configured to generate gate control signals to control the conduction state of the SR switches so that the body diode conduction time is minimized and a negative current across the SR switches is reduced or eliminated. The method includes controlling the conduction state of SR switches to conduct as the body diode associated with the switch begins to conduct and controlling the SR switch to turn off as the current through the switch approaches a zero crossing.

Abstract: The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.

Abstract: This application discusses methods and apparatus for a data-on-supply repeater. In an example, a repeater can include a repeater circuit configured to receive a power signal at an input and to provide a representation of a received analog data signal at an output, a direction detector configured to receive the power signal from a first bus conductor of a plurality of bus conductors, to identify the first buss conductor of the plurality of bus conductors as a transmitting conductor, and to provide an output indicative of the transmitting conductor, a first input multiplexer configured to couple the transmitting conductor to the input of the repeater circuit in response to the output of the direction detector, and an output multiplexer configured to couple the output of the repeater circuit to a second bus conductor of the plurality of bus conductors, wherein the second bus conductor is different than the transmitting conductor.

Abstract: This document discusses, among other things, voltage converters and computed on-time voltage converters. In an example, an on-time generator for a voltage converter can include a timing capacitor configured to provide a timing voltage, a comparator configured to receive the timing voltage and a threshold voltage and to provide the timing signal using a comparison of the timing voltage and the threshold voltage, a current source configured to discharge the timing voltage of the timing capacitor after a start-up delay, and first and second compensation capacitors configured to bias the timing voltage of the timing capacitor to compensate for the start-up delay.

Abstract: An apparatus includes a MEMS gyroscope sensor including a first sensing capacitor and a second sensing capacitor and an IC. The IC includes a switch circuit configured to electrically decouple the first sensing capacitor from a first input of the IC and electrically couple the second sensing capacitor to a second input of the IC, and a capacitance measurement circuit configured to measure capacitance of the second sensing capacitor of the MEMS gyroscope sensor during application of a first electrical signal to the decoupled first capacitive element.

Abstract: This document discusses, among other things, an inertial sensor including a single proof-mass formed in an x-y plane of a device layer, the single proof-mass including a single, central anchor configured to suspend the single proof-mass above a via wafer. The inertial sensor further includes first and second electrode stator frames formed in the x-y plane of the device layer on respective first and second sides of the inertial sensor, the first and second electrode stator frames symmetric about the single, central anchor, and each separately including a central platform and an anchor configured to fix the central platform to the via wafer, wherein the anchors for the first and second electrode stator frames are asymmetric along the central platforms with respect to the single, central anchor.

Abstract: An apparatus comprises a first connector, a second connector, a detection circuit and a logic circuit. The first connector and the second connector are configured for electrical communication with first and second conducting terminals, respectively, of an audio jack plug. The detection circuit is configured to apply a first value of current to the first connector, and apply a second value of current to the second connector. The logic circuit is configured to generate an indication that the audio jack plug is fully inserted according to a logic level detected at the second connector when electrical ground is detected at the first connector.