Abstract: A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

Abstract: In a gate electrode, above a first polycrystalline silicon film, a second polycrystalline silicon film, which has a predetermined silicon crystal face orientation directed with respect to and is smaller in crystal diameter than the first polycrystalline silicon film, is provided, so that even if there locally exist portions which are different in silicidization speed in forming a silicide layer in the second polycrystalline silicon film, the silicidization reaction with unreacted portions of the second polycrystalline silicon film can occur faster than the silicidization reaction with the first polycrystalline silicon film.

Abstract: A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.

Abstract: The present invention discloses methods and systems of accomplishing I/O-based redundancy for a memory device that includes two-bit memory cells. The memory device includes a core two-bit memory cell array and a redundant two-bit memory cell array. The configuration of the core two-bit memory cell array is non-uniform such that the two-bit memory cells therein are not arranged in a sequential order. Due to the non-uniform configuration, I/O based redundancy is accomplished by decoding the addresses with a redundant Y-decoder circuit and translating the addresses using an address translation circuit. The translated addresses identify the location of the two-bit memory cells within the non-uniform core two-bit memory cell array. The decoding of the addresses configures the redundant two-bit memory cell array to provide a configuration that matches the two-bit memory cells in the location identified by the translated address.

Abstract: One aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device.

Abstract: Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.

Abstract: A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.

Abstract: A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

Abstract: A silicon nitride film for storing electric charge is formed on a semiconductor substrate while placing a tunnel oxide film in between, and the silicon nitride film is then subjected to hydrogen plasma treatment so as to effectively erase unnecessary charge stored therein during various process steps in fabrication of the semiconductor memory device, to thereby stabilize the threshold voltage (Vth) of the semiconductor memory device.

Abstract: A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure which is lower than the first pressure; and the step of further depositing the insulation film 32b with the second pressure set in the deposition chamber. The insulation film is deposited with the first pressure a little lower than a second pressure set in a deposition chamber, and the insulation film is further deposited with the second pressure lower than the first pressure set in the deposition chamber. Furthermore, the insulation film is not deposited in the state where the pressure in the deposition chamber is extremely low, and an atmosphere in the deposition chamber is unstable. Thus, a semiconductor device having the insulation film with a sufficiently flat surface can be fabricating without using reflow process.

Abstract: The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.

Abstract: One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states.