Patents Assigned to FED Corporation
  • Patent number: 6198214
    Abstract: In order to operate Field Emission Displays (“FEDs”) contain an evacuated space. Generally, two soda-lime glass substrates, separated by a vacuum gap, act as cathode and anode. The vacuum gap is essential for the electrons to be emitted from the sharp cathode tips and travel towards the anode to give up their energy to the phosphor anode plate to emit light. The two plates and the frit seal holding the vacuum gap are under strain due to the atmospheric pressure acting on them. For small size FEDs , this strain is not a problem. However, for large area FEDs, the strain is detrimental both to the glass plates (2 mm thick) and frit seal. Under the strain, both the cathode and anode plates will buckle-in towards vacuum and, in turn, stress the frit seal, causing cracks and vacuum failure. To minimize this effect and enable the FED to operate normally, a field emissive display with a support plate for the cathode plate is disclosed.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: March 6, 2001
    Assignee: FED Corporation
    Inventors: Munisamy Anandan, Olivier Prache
  • Patent number: 6069443
    Abstract: The present invention is directed to an organic light emitting device having a substrate, and at least one conductor formed on the substrate. A first insulator layer is formed on the at least one conductor and the substrate. The insulator layer includes at least one pixel opening formed therein defining a pixel area. A second insulator layer is formed on the first insulator layer. The organic light emitting device also include an OLED layer formed on the at least one conductor in the pixel area. The organic light emitting device may further include a sealing structure formed over the OLED layer. The sealing structure includes at least one material formed over the OLED layer. The first insulator layer and the sealing structure form a protective barrier around the OLED layer. The first insulator layer includes a uniformly sloping surface surrounding the pixel area. The OLED layer preferably extends over the uniformly sloping surface.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: May 30, 2000
    Assignee: FED Corporation
    Inventors: Gary W. Jones, Amalkumar P. Ghosh
  • Patent number: 6060728
    Abstract: Isolation structures and means for isolating the electron injectors in an organic light emitting device are disclosed. The isolation structures may reduce the likelihood of electrical shorts or cross-talks between adjacent columns of electron injector material. The isolation structures may comprise multiple layers of distinct material, including a layer of organic insulation material, such as photoresist or other hydrophobic organic material. The insulation material may be spin or extrusion coated onto the device. The insulation material may be sandwiched between inorganic oxide layers. The insulation material may be selected such that it is capable of being preferentially etched relative to the oxide layers by dry etching methods such as oxygen plasma. Alternatively, the insulation material may be made of material that does not have a very strong adhesion to an underlying oxide layer, so that the insulation material and any conductive material formed on top of it may be removed using a tape lift-off process.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: May 9, 2000
    Assignee: FED Corporation
    Inventors: Amalkumar P. Ghosh, Gary W. Jones
  • Patent number: 6027388
    Abstract: A mask structure may be formed on a field emitter substrate for use in forming emitter wells on and in the substrate. The mask structure may be formed from a multilayered structure on the surface of the substrate using a laser lithography process. From the substrate up, the multilayered structure may include an antireflective coating, a photoresistive layer, an optional etch resistant layer between the antireflective coating and the photoresistive layer, and an optional second antireflective coating between the optional etch resistant layer and the photoresistive layer. The pattern of the mask structure may be transferred to the multilayer structure by exposing the photoresistive layer to laser light. The antireflective coatings may reduce the amount of stray laser light that reflects off the substrate and onto the back of the photoresistive layer.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: February 22, 2000
    Assignee: Fed Corporation
    Inventors: Gary W. Jones, Susan K. Jones, Amalkumar P. Ghosh
  • Patent number: 6023259
    Abstract: The present invention is a current driver for an active matrix organic light emitting device display. As embodied herein, the driver relies upon a single transistor, driven in a saturation regime to provide a current source for an OLED. This results in a pulse drive. The driver of the present invention is compatible with high speed integrated drivers and can be fabricated on the same substrate as the OLED. A technique for driving an OLED is disclosed that will produce a good quality gray scale image.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: February 8, 2000
    Assignee: Fed Corporation
    Inventors: Webster E. Howard, Olivier Prache
  • Patent number: 6016033
    Abstract: The present invention is directed to an electrode structure for an organic light-emitting device display. The electrode structure includes a transparent electrode and a high conductivity rib. The structure provides top side light output and a low line resistance, and enables a high resolution display. The structure permits a display to be built on top of a silicon driver chip for active matrix addressing.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: January 18, 2000
    Assignee: Fed Corporation
    Inventors: Gary W. Jones, Webster E. Howard, Steven M. Zimmerman
  • Patent number: 6010918
    Abstract: Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: January 4, 2000
    Assignee: FED Corporation
    Inventors: Jeffrey R. Marino, Joseph K. Ho
  • Patent number: 5965898
    Abstract: A high aspect ratio gated emitter structure and a method of making the structure are disclosed. Emitters may be provided in a densely packed array on a support. Two distinct layers of insulator material may surround the emitters. The lower layer of insulator material may be a non-conformally applied spray-on or spin-on insulator. The non-conformal insulator material may pool at the base regions of the emitters so that the tip regions of the emitters extend out of the lower layer of insulator material. The upper layer of insulator material is applied to the lower layer using a conformal process so that the tip regions of the emitters are covered by the upper layer of insulator material. Gate material is applied to the upper layer of insulator material. Holes are provided in the gate material over the tip regions and wells are provided in the upper layer of insulator material surrounding the tip regions.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: October 12, 1999
    Assignee: FED Corporation
    Inventors: Gary W. Jones, Steven M. Zimmerman
  • Patent number: 5959725
    Abstract: A large area energy beam intensity profiler and method of profiling are disclosed. The profiler includes intensity detectors which generate electrical signals corresponding to the intensity of the beam. The output of the detectors is processed by a computer and displayed on a monitor. The invention provides for adjustment of the beam in response to a nonuniform intensity profile, or an indication that the beam is misaligned.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: September 28, 1999
    Assignee: Fed Corporation
    Inventor: Amalkumar P. Ghosh
  • Patent number: 5920080
    Abstract: An organic light emitting device ("OLED") for a color video display. The OLED is a layered structure formed on a substrate. A layer of light emitting organic material is sandwiched between two conductive layers and placed on the substrate. Overlying the conductors and organic layer is a transparent cover layer. The OLED of the present invention includes an innovative microcavity enhancing structure, which restricts light emission in directions parallel to the substrate and provides increased light output toward the viewer.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: July 6, 1999
    Assignee: Fed Corporation
    Inventor: Gary W. Jones
  • Patent number: 5903243
    Abstract: An imaging apparatus for providing an image from a display to an observer, comprising: a display generating an optical output, an imaging surface member constructed and arranged for viewing by said observer, and a scanning mirror/lens assembly optically interposed between the display and the imaging surface member, and constructed and arranged to motively repetitively scan the display, generate a scanned image, and transmit the scanned image to the imaging surface member, for viewing of the scanned image. Various field emitter display designs and subassemblies are described, which may be usefully employed in such imaging apparatus.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: May 11, 1999
    Assignee: Fed Corporation
    Inventor: Gary W. Jones
  • Patent number: 5903098
    Abstract: A field emitter array device includes a ceramic substrate member having a multiplicity of through conductive vias therein. An insulative material layer is located on the ceramic substrate member. An addressable array of gate and emitter line elements is located on the insulative material and is conductively coupled to the through substrate conductive vias. A backside connector is located on the ceramic substrate member and conductively coupled to the vias for connection of the ceramic substrate member with an array driver device for the addressable array of emitter and gate line elements. A field emitter array of field emitter elements on the insulative material layer of the ceramic substrate member which are operatively coupled with the addressable array of gate and emitter line elements.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: May 11, 1999
    Assignee: FED Corporation
    Inventor: Gary W. Jones
  • Patent number: 5886460
    Abstract: A field emitter device formed by a veil process wherein a protective layer comprising a release layer is deposited on the gate electrode layer for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity in the dielectric material layer on a substrate, and during the formation of a field emitter element in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: March 23, 1999
    Assignee: FED Corporation
    Inventors: Gary W. Jones, Steven M. Zimmerman, Jeffrey A. Silvernail, Susan K. Schwartz Jones
  • Patent number: 5869169
    Abstract: A field emitter element comprising a bottom layer of material shaping the overall emitter element, and a top layer of low work function material or otherwise of high electron emissivity characteristic. The low work function top layer preferably is shaped to a sharp point. The bottom layer may be formed of a material such as tantalum, molybdenum, gold, or silicon (or alloys thereof), and the top layer may be formed of a material such as Cr.sub.3 Si, Cr.sub.3 Si.sub.2, CrSI.sub.2, Nb.sub.3 Si.sub.2, Nb, Cr.sub.2 O.sub.3 or SiC. In a specific aspect, at least one of the first and second emitter materials is chromium oxide (Cr.sub.2 O.sub.3). In another variant, the first emitter material is an insulator of leaky dielectric, e.g., SiO with a 10-60% Cr by weight based on the weight of SiO, and the second emitter material is SiO+50-90% Cr by weight, based on the weight of SiO.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: February 9, 1999
    Assignee: FED Corporation
    Inventor: Gary W. Jones
  • Patent number: 5866978
    Abstract: An integral and internal matrix getter structure for capturing residual gas in a vacuum sealed container is disclosed. The vacuum sealed container may be a flat panel display having a small vacuum gap between two closely spaced panels. The getter structure may be provided on the inside of the walls of the display. In particular, the getter structure may be provided between phosphor groups and/or between field emitter groups on the display panels. The getter structure may be sealed to avoid exposure of the getter material until after a vacuum condition is reached within the display. Activation of the getter structure may be provided by selectively heating the getter structure with a laser or with resistive heating elements underlying the getter structure. Methods of making the getter structure are also disclosed.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 2, 1999
    Assignee: Fed Corporation
    Inventors: Gary W. Jones, Amalkumar P. Ghosh, Steven M. Zimmerman, Munisamy Anandan
  • Patent number: 5844351
    Abstract: A field emitter device formed by a veil process wherein a protective layer comprising a release layer is deposited on the gate electrode layer for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity in the dielectric material layer on a substrate, and during the formation of a field emitter element in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: December 1, 1998
    Assignee: Fed Corporation
    Inventors: Gary W. Jones, Steven M. Zimmerman, Jeffrey A. Silvernail, Susan K. Schwartz Jones
  • Patent number: 5828163
    Abstract: A field emitter device includes a column conductor, an insulator, and a resistor structure for advantageously limiting current in a field emitter array. A wide column conductor is deposited on an insulating substrate. An insulator is laid over the column conductor. A high resistance layer is placed on the insulator and is physically isolated from the column conductor. The high resistance material may be chromium oxide or 10%-50% wt % Cr+SiO. A group of microtip electron emitters is placed over the high resistance layer. A low resistance strap interconnects the column conductor with the high resistance layer to connect in an electrical series circuit the column conductor, the high resistance layer, and the group of electron emitters. One or more layers of insulator and a gate electrode, all with cavities for the electron emitters, are laid over the high resistance material. One layer of insulator is selected from a group of materials including SiC, SiO, and Si.sub.3 N.sub.4.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: October 27, 1998
    Assignee: FED Corporation
    Inventors: Gary W. Jones, Susan K. Jones, Jeffrey Marino, Joseph K. Ho, R. Mark Boysel, Steven M. Zimmerman, Yachin Liu, Michael J. Costa, Jeffrey A. Silvernail
  • Patent number: 5828288
    Abstract: A microelectronic field emitter device comprising a substrate, a conductive pedestal on said substrate, and an edge emitter electrode on said pedestal, wherein the edge emitter electrode comprises an emitter cap layer having an edge. The invention also contemplates a current limiter for a microelectronic field emitter device, which comprises a semi-insulating material selected from the group consisting of SiO, SiO+Cr (0 to 50% wt.), SiO2+Cr (0 to 50% wt.), SiO+Nb, Al2O3 and SixOyNz sandwiched between an electron injector and a hole injector. Another aspect of the invention relates to a microelectronic field emitter device comprising a substrate, an emitter conductor on such substrate, and a current limiter stack formed on said substrate, such stack having a top and at least one edge, a resistive strap on top of the stack, extending over the edge in electrical contact with the emitter conductor; and an emitter electrode on the current limiter stack over the resistive strap.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: October 27, 1998
    Assignee: Fed Corporation
    Inventors: Gary W. Jones, Steven M. Zimmerman, Susan K. Schwartz Jones, Michael J. Costa, Jeffrey A. Silvernail
  • Patent number: 5788550
    Abstract: A spacer structure for use in a flat panel display, and a corresponding flat panel display article are disclosed, together with an appertaining method of fabricating the spacer structure utilizing a photosensitive precursor material which is selectively irradiated, developed and etchingly processed to produce shaped standoff elements for a unitary spacer structure. The spacer structure may be dimensionally fabricated to precisely align with a selected pixel region, comprising a single pixel or an array of pixels, e.g., a color (red, blue, green) triad.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: August 4, 1998
    Assignee: FED Corporation
    Inventors: Gary W. Jones, Steven M. Zimmerman
  • Patent number: 5771098
    Abstract: An interferometric lithographic apparatus includes an arrangement for applying interfering laser beams to a part for producing a first interference pattern. The first interference pattern has a first fringe spacing. A mobile part holder stage is repositioned to change the interference pattern and produce a second fringe spacing. A control arrangement, automatically responsive to the repositioning of the part holder, re-aligns optical paths and optimally interferes the laser beams to produce the second fringe spacing.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: June 23, 1998
    Assignee: Fed Corporation
    Inventors: Amalkumar P. Ghosh, Susan K. Schwartz Jones, Gary W. Jones, Steven M. Zimmerman, Yachin Liu