Abstract: A stacked switch includes two or more individual network switches connected to each other in a ring or daisy chain topology over stacking links, and at least one port on two or more of the individual switches comprising the stacked switch is a member of a LAG configured on the stacked switch. Each of the individual switches comprising the stacked switch include control plane and data plane functionality that operates to maintain switching tables and to process network data ingressing to the switch to determine how to forward the network data through the switch to an egress point. The control functionality included in each of the switches comprising the stacked switch also includes an enhanced ECMP functionality that operates to optimize the use of stacking link bandwidth on the stacking links connecting the two or more individual switches to each other.

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract: A data communication network includes a client device and multiple aggregation devices coupled to each other and the client via links within a link aggregation group (“LAG”) across the aggregation devices. The aggregation devices appear to the client as a single device coupled thereto, and operate in conjunction with each other by assigning at least one different identifier to each of the plurality of separate aggregation devices and storing information including the identifiers to association tables located on each of the aggregation devices. The multiple aggregation devices can be separate switches, and the LAG can include multiple ports across the switches, with a different identifier being assigned to each of the ports in the LAG. A virtual link trunk interface can couple aggregation devices, which can reconfigure communication paths thereacross with respect to the client device using the identifiers in the stored association tables when a LAG link fails.

Abstract: A financial market data network having a lowered overall latency includes communication interfaces, specialized switches having internal switching fabric, and feed handlers that all facilitate communications between financial exchanges and consumers of financial market data therefrom. A feed handler is situated within or proximate a specialized switch and is arranged to receive raw financial market data directly from financial exchanges without the data first traveling through any switching fabric. The feed handler is adapted to process the received raw financial market data into a normalized format before the normalized financial market data is ever routed through any switching fabric, prior to being sent to consumers. The communication interfaces can include I/O ports located on the specialized switches, and the feed handlers can include one or more computer processors or servers.

Abstract: Two network switches are configured in a stacked relationship to each other and include link aggregation sub-layer functionality. Switching tables are programmed on each switch with information used to forward packets ingressing to them over a redundant LAG that is identified in the switching table by a port that is a member of the redundant LAG.

Abstract: Methods and apparatus for serial channel operation are disclosed. An N+1-level signaling scheme is used to transmit N staggered but overlapping NRZ sub-sequences concurrently on a serial channel. Each sequence has a bit rate R and an essential bandwidth of R Hz. The combined bit rate of the channel is N×R, but due to a lack of correlation between the sub-sequences, the essential bandwidth remains approximately R Hz. The signaling scheme also contains redundancy that allows some errors to be detected and/or corrected. Other embodiments are also described and claimed.

Abstract: A LAN includes a router that is connected to two or more racks of servers and each of the servers can support a plurality of virtual machines. The router is configured to forward data packets based on IP destination addresses or based on destination MAC addresses and builds and maintains forwarding tables in support of data packet forwarding in the layer 3 and the layer 2 network environment. In support of layer 2 forwarding, the router builds and maintains an aggregated MAC switching table that is comprise of a subset of the table entries typically needed to switch packets to their destination, and in support of layer 3 forwarding, the router or switch builds and maintains an aggregated ARP forwarding table that is comprised of a subset of the table entries typically needed to forward packets to their destination.

Abstract: A packet switch contains a link state group manager that forms supergroups from multiple link aggregations. The link state group manager collects state information for the link aggregations in a supergroup, and uses state criteria to determine whether the link aggregations are allowed to be up, as a supergroup, for data traffic. This allows a supergroup of links to only come up when it meets a minimum performance criteria, with traffic routed around the supergroup when the supergroup cannot meet the minimum performance criteria, even if some link aggregations in the group are functional.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: A network switch is comprised of a control processor and one or more line cards. The control processor includes functionality to register interest with a hypervisor, operating in conjunction with a network host connected to the switch, in data object attributes maintained on the network host by the hypervisor. The hypervisor associated with the network host sends changes in the host attributes to the switch which the switch maintains in a listing of attributes. The switch traps and copies particular packets to the switch control processor where a provisioning function operates on the attribute information in the list with source information included in the packet header in order to configure a forwarding table on the line card.

Abstract: A packet network system, such as an autonomous system, includes a plurality of packet network devices some of which are edge routers and some of which are core routers. Each of the edge and core routers include functionality that operates to receive network traffic, process the traffic as needed and to forward the traffic to its destination. Additionally, each router includes a traffic distribution function that operates to calculate path bandwidths for all of the paths over which the traffic can be forwarding through the system and to use the volume of traffic ingressing to the system, link utilization information and the calculated path bandwidth to redistribute the traffic in the system such that traffic loss in the system in minimized.

Abstract: A packet network device, such as a router or switch, includes functionality that operates to receive network traffic, process the traffic as needed and to forward the traffic to its destination. Additionally, each router includes a weighted equal cost multipath routing function that operates to identify equal cost paths over which to forward the network traffic, to calculate a path weighting that is dependent upon the path bandwidth and to forward the traffic ingressing to it over each of the equal cost paths according to the calculated path weighting.

Abstract: Methods of operating a packet network device having multiple serial channels crossing a backplane are disclosed. In at least one embodiment, a management function performs dynamic modifications to the packet network device configuration in response to detected backplane errors. These modifications can directly alter a characteristic of a channel that is generating errors, or can indirectly affect such a channel by directly altering a characteristic of an “aggressor” channel that is indicated as producing crosstalk on that channel. Other embodiments are also described and claimed.

Abstract: A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Abstract: A standoff joins a circuit board to a chassis member using a rivet. The standoff has a cap surface with a hole that allows the body of an unexpanded blind rivet to pass into an inner cavity of the standoff. The rivet is then expanded against the underside of the cap. In use, the standoff rests against the underside of a circuit board, and the rivet passes through a hole in the circuit board and into the standoff. The rivet head engages the circuit board to hold the circuit board against the standoff.

Abstract: An autonomous system includes at least some packet network devices that are capable of operating in a virtual route aggregation environment and some packet network devices that are not capable of operating in a virtual route aggregation environment. The autonomous system includes at least one egress border router, at least one aggregation router and at least one intermediate router. The egress border router uses an interior border gateway protocol to distribute a label message to the other routers in the autonomous system, the label message including a next hop MAC address associated with either an external router or the egress border router. The egress border router and the intermediate router using information included in the label message to contrast layer 2 table entries and the aggregation router using information included in the label message to construct a layer 3 table entry.

Abstract: A modular packet network device has a chassis in which multiple logic cards mate to the front side of an electrical signaling backplane. Logic power for the logic cards is supplied from a group of power converter cards that convert primary power to the logic voltages required by the logic cards. The power converter cards lie in a separate cooling path behind the backplane. Advantages achieved in at least some of the embodiments include removing primary power planes from the signaling backplane or portion of the backplane, providing redundant, upgradeable power modules whose individual failure does not cause logic card failure, and providing cool air to power converter circuits that would be subject to only heated air if located on the logic cards. Other embodiments are also described and claimed.

Abstract: A network processing device, such as a router, is implemented in a thin form factor chassis that encloses a primary printed circuit board. The router chassis has elongated openings on its top surface that permit access to connectors mounted on the printed circuit board. The printed circuit board includes all of the necessary electronic components that operate to receive, process, and transmit information over the network.

Abstract: Systems, methods, and apparatuses are provided that enable streaming of ATM cells between a transmit/receive data processing application and a transmission convergence function. Data to be segmented into an ATM cell is received at a SAR engine, and provided to a transmission convergence function, with the first cells transmitted to the transmission convergence function before the SAR function receives an end-of-packet indication from the optimization engine. Data received at a transmission convergence function is placed in a received packet queue at the SAR function, with packets provided to an application after a start-of-packet indication is received, and before an end-of-packet indication is received, at the SAR function.

Abstract: A multiprocessor system includes multiple processors executing multiple processes that send messages to each other. The system uses a connectionless single-window inter-process communication (IPC) protocol to avoid the high message-processing overhead of a connection-based protocol like TCP. The IPC protocol uses a central message-receive service that runs in the kernel on each processor to handle error-checking and sequence number checking and acknowledge received messages, while the single-window mechanism avoids out-of-order message reordering/buffering complexity. Since each process sending a message does not need to wait for the receiving process (which may be otherwise preoccupied or not even the focus of the receiving processor when the message is received and queued) before receiving acknowledgments, the protocol greatly reduces single-window message latency for all processes without resorting to complex connection-based multi-packet transmission windows.