Patents Assigned to FormFactor
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Publication number: 20070205780Abstract: Systems and methods for providing a stack with a guard plane embedded in the stack are disclosed. An electrical apparatus can be made by forming a stack comprising an electrically conductive signal structure, an electrical guard structure, and an electrically insulating structure disposed between the signal structure and the guard structure. The signal structure, insulating structure, and guard structure can be aligned one with another in the stack.Type: ApplicationFiled: March 6, 2006Publication date: September 6, 2007Applicant: FORMFACTOR, INC.Inventor: Benjamin Eldridge
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Patent number: 7262611Abstract: A wiring substrate can include a substrate material, which can have a first surface and a second surface. A plurality of first electrically conductive elements can be disposed on the first surface, and a plurality of second electrically conductive elements can be disposed on the second surface. Ones of the first conductive elements can be electrically connected through the substrate material to ones of the second conductive elements. A mechanism can be located in a first region, which can be a center region, of the second surface of the substrate material. The mechanism can be configured to engage a control member. First activation of the control member can apply an adjustable pulling force to the first region, and second activation of the control member can apply an adjustable pushing force to the first region. The mechanism can be or can include a threaded stud, and the control member can be or can include a threaded nut configured to engage the threaded stud.Type: GrantFiled: May 24, 2004Date of Patent: August 28, 2007Assignee: FormFactor, Inc.Inventors: Gaetan L. Mathieu, Benjamin N. Eldridge, Gary W. Grube
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Patent number: 7262624Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.Type: GrantFiled: December 21, 2004Date of Patent: August 28, 2007Assignee: FormFactor, Inc.Inventor: Charles A. Miller
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Publication number: 20070194779Abstract: An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.Type: ApplicationFiled: April 17, 2007Publication date: August 23, 2007Applicant: FORMFACTOR, INC.Inventor: Benjamin Eldridge
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Patent number: 7257796Abstract: A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics.Type: GrantFiled: January 18, 2005Date of Patent: August 14, 2007Assignee: FormFactor, Inc.Inventors: Charles A. Miller, John M. Long
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Patent number: 7253651Abstract: A central test facility transmits wirelessly test data to a local test facility, which tests electronic devices using the test data. The local test facility transmits wirelessly response data generated by the electronic devices back to the central test facility, which analyzes the response data to determine which electronic devices passed the testing. The central test facility may provide the results of the testing to other entities, such as a design facility where the electronic devices were designed or a manufacturing facility where the electronic devices where manufactured. The central test facility may accept requests for test resources from any of a number of local test facilities, schedule test times corresponding to each test request, and at a scheduled test time, wirelessly transmits test data to a corresponding local test facility.Type: GrantFiled: December 21, 2004Date of Patent: August 7, 2007Assignee: FormFactor, Inc.Inventors: Igor Y. Khandros, Benjamin N. Eldridge
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Patent number: 7251884Abstract: A robust mechanical structure is provided to prevent small foundation structures formed on a substrate from detaching from the substrate surface. The strengthened structure is formed by plating a foundation metal layer on a seed layer and then embedding the plated foundation structure in an adhesive polymer material, such as epoxy. Components, such as spring probes, can then be constructed on the plated foundation. The adhesive polymer material better assures the adhesion of the metal foundation structure to the substrate surface by counteracting forces applied to an element, such as a spring probe, attached to the plated foundation.Type: GrantFiled: April 26, 2004Date of Patent: August 7, 2007Assignee: FormFactor, Inc.Inventors: Gary W. Grube, Gaetan L. Mathieu, Benjamin N. Eldridge, Chadwick D. Sofield
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Patent number: 7245139Abstract: A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads.Type: GrantFiled: April 27, 2004Date of Patent: July 17, 2007Assignee: FormFactor, Inc.Inventor: Charles A. Miller
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Patent number: 7245137Abstract: A test head assembly can include a probe card, which can include first contact areas. The test head assembly can also include a contactor, which can include second contact areas. An interposer can include first spring contact structures and second spring contact structures. The first spring contact structures can contact one of the first contact areas, and the second spring contact structures can contact one of the second contact areas. Ones of the first spring contact structures can be electrically connected through the interposer to ones of the second spring contact structures. One of the first spring contact structures can include a pair of contacts, both of which can extend from a first surface of the interposer to contact one of the first contact areas. Alternatively or additionally, one of the second spring contact structures can include a pair of contacts, both of which can extend form a second surface of the interposer to contact one of the second contact areas.Type: GrantFiled: May 2, 2005Date of Patent: July 17, 2007Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Stuart W. Wenzel
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Patent number: 7245134Abstract: A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program.Type: GrantFiled: January 31, 2005Date of Patent: July 17, 2007Assignee: FormFactor, Inc.Inventors: Dane C. Granicher, Roy J. Henson, Charles A. Miller
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Patent number: 7245120Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.Type: GrantFiled: September 27, 2005Date of Patent: July 17, 2007Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Charles A. Miller
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Publication number: 20070152685Abstract: Probe array structures and methods of making probe array structures are disclosed. A plurality of electrically conductive elongate contact structures disposed on a first substrate can be provided. The contact structures can then be partially encased in a securing material such that ends of the contact structures extend from a surface of the securing material. The exposed portions of the contact structures can then be captured in a second substrate.Type: ApplicationFiled: January 3, 2006Publication date: July 5, 2007Applicant: FormFactor, Inc.Inventors: Benjamin Eldridge, Treliant Fang, John Gritters, Igor Khandros, Dennis Ma, Gaetan Mathieu
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Patent number: 7238464Abstract: SU-8 photoresist compositions are modified to improve their adhesion properties by adding 1% to 6% of an adhesion promoter selected from the group consisting of glycidoxypropanetrimethoxysilane, mercaptopropyltrimethoxysilane, and aminopropyltrimethoxysilane. SU-8 photoresist compositions are modified to improve their resistance to cracking and film stress by adding 0.5% to 3% of a plasticizer selected from the group consisting of dialkylphthalates, dialkylmalonates, dialkylsebacates, dialkyladipates, and diglycidyl hexahydrophthalates. The improvements can be obtained simultaneously by adding both the adhesion promoter and the plasticizer to SU-8 photoresist compositions.Type: GrantFiled: February 27, 2006Date of Patent: July 3, 2007Assignee: FormFactor, Inc.Inventor: Treliant Fang
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Patent number: 7239971Abstract: A periodic signal is driven onto a transmission line, and the frequency of the periodic signal is varied from an initial frequency that corresponds to a quarter wave or half wave of an estimated length of the transmission line. A null or a peak in the envelope of the voltage or current wave induced on the transmission line by the periodic signal is detected at or near the end of the transmission line onto which the signal is driven. The frequency of the periodic signal that caused the null or peak may be used to calculated the length of the transmission line or a propagation delay through the transmission line. A plurality of transmission lines may be deskewed by determining the propagation delay through each transmission line and adjusting a variable delay in each transmission line so that the transmissions lines approximately equal overall propagation delays.Type: GrantFiled: April 16, 2004Date of Patent: July 3, 2007Assignee: FormFactor, Inc.Inventor: Charles A. Miller
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Patent number: 7239220Abstract: A transmission line includes a signal conductor and at least one varactor diode capacitively coupled to the signal conductor. The transmission line's signal path delay is a function of its shunt capacitance, and the varactor's capacitance forms a part of the transmission line's shunt capacitance. The transmission line's signal path delay is adjusted by adjusting a control voltage across the varactor diode thereby to adjust the varactor diode's capacitance.Type: GrantFiled: June 6, 2006Date of Patent: July 3, 2007Assignee: FormFactor, Inc.Inventor: Charles A. Miller
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Patent number: 7239159Abstract: An apparatus for determining a planarity of a first structure configured to hold a probing device to the planarity of a second structure configured to hold a device to be probed is disclosed. In one example of the apparatus, a plurality of moveable push rods are disposed in a substrate, which is attached to the first structure. In initial non-displaced positions, the push rods correspond to a planarity of the first structure. The second structure is then brought into contact with the push rods, displacing the push rods into second positions that correspond to a planarity of the second structure. In another example of the apparatus, beams of light are reflected off of reflectors disposed on the first structure and onto sensors disposed on the second structure. The locations of the reflected beams on the sensors are noted and used to determine the planarity of the first structure with respect to the second structure.Type: GrantFiled: February 1, 2005Date of Patent: July 3, 2007Assignee: FormFactor, Inc.Inventors: Gary W. Grube, Thomas N. Watson
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Publication number: 20070139061Abstract: A probing apparatus can comprise a substrate, conductive signal traces, probes, and electromagnetic shielding. The substrate can have a first surface and a second surface opposite the first surface, and the electrically conductive first signal traces can be disposed on the first surface of the first substrate. The probes can be attached to the first signal traces, and the electromagnetic shielding structures can be disposed about the signal traces.Type: ApplicationFiled: December 1, 2006Publication date: June 21, 2007Applicant: FORMFACTOR, INC.Inventors: Benjamin Eldridge, Carl Reynolds, Takao Saeki, Yoichi Urakawa
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Publication number: 20070141743Abstract: Systems and methods for depositing a plurality of droplets in a three-dimensional array are disclosed. The array can comprise a first type of droplets disposed to form a support structure and a second type of droplets forming a conductive seed layer on the support structure. A structure material can be electrodeposited onto the seed layer to create a three-dimensional structure.Type: ApplicationFiled: December 21, 2005Publication date: June 21, 2007Applicant: FORMFACTOR, INC.Inventors: Gaetan Mathieu, Treliant Fang, Eric Hobbs
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Patent number: 7230437Abstract: A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, and unpluggable using pins, enabling movement over a range of positions.Type: GrantFiled: June 15, 2004Date of Patent: June 12, 2007Assignee: FormFactor, Inc.Inventors: Benjamin N. Eldridge, Barbara Vasquez, Makarand S. Shinde, Gaetan L. Mathieu, A. Nicholas Sporck
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Publication number: 20070126440Abstract: A probe card assembly can comprise a probe head assembly and a wiring substrate. The probe head assembly can comprise a plurality of probes disposed to contact an electronic device disposed on a holder in a test housing. The wiring substrate can include an electrical interface to a test controller and a plurality of electrical wiring composing electrical paths between the electrical interface and ones of the probes, and the wiring substrate can comprise a first portion on which the electrical interface is disposed and a second portion composing the probe head assembly. The second portion of the wiring substrate can be moveable with respect to the first portion of the wiring substrate.Type: ApplicationFiled: October 20, 2006Publication date: June 7, 2007Applicant: FORMFACTOR, INC.Inventors: Eric Hobbs, Alexander Slocum, Benjamin Eldridge, Keith Breinlinger, Shawn Powell