Abstract: A thermal adjustment apparatus for adjusting one or more thermally induced movements of an electro-mechanical assembly includes: a compensating element expanding at a first rate different from a second rate at which the electro-mechanical assembly expands for generating a counteracting force in response to changes in temperature; and a coupling mechanism coupling the compensating element to the electro-mechanical assembly, and being adjustable to control an amount of the counteracting force applied to the electro-mechanical assembly as temperature changes.

Abstract: SU-8 photoresist compositions are modified to improve their adhesion properties by adding 1% to 6% of an adhesion promoter selected from the group consisting of glycidoxypropanetrimethoxysilane, mercaptopropyltrimethoxysilane, and aminopropyltrimethoxysilane. SU-8 photoresist compositions are modified to improve their resistance to cracking and film stress by adding 0.5% to 3% of a plasticizer selected from the group consisting of dialkylphthalates, dialkylmalonates, dialkylsebacates, dialkyladipates, and diglycidyl hexahydrophthalates. The improvements can be obtained simultaneously by adding both the adhesion promoter and the plasticizer to SU-8 photoresist compositions.

Abstract: The present invention discloses a method and system compensating for thermally induced motion of probe cards used in testing die on a wafer. A probe card incorporating temperature control devices to maintain a uniform temperature throughout the thickness of the probe card is disclosed. A probe card incorporating bi-material stiffening elements which respond to changes in temperature in such a way as to counteract thermally induced motion of the probe card is disclosed including rolling elements, slots and lubrication. Various means for allowing radial expansion of a probe card to prevent thermally induced motion of the probe card are also disclosed. A method for detecting thermally induced movement of the probe card and moving the wafer to compensate is also disclosed.

Abstract: An image of an array of probes is searched for alignment features. The alignment features are then used to bring contact targets and the probes into contact with one another. The alignment features may be a feature of one or more of the tips of the probes. For example, such a feature may be a corner of one of the tips. An array of probes may be formed to have such alignment features.

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

Abstract: A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract: An interconnection element of a spring (body) including a first resilient element with a first contact region and a second contact region and a first securing region and a second resilient element, with a third contact region and a second securing region. The second resilient element is coupled to the first resilient element through respective securing regions and positioned such that upon sufficient displacement of the first contact region toward the second resilient element, the second contact region will contact the third contact region. The interconnection, in one aspect, is of a size suitable for directly contacting a semiconductor device. A large substrate with a plurality of such interconnection elements can be used as a wafer-level contactor. The interconnection element, in another aspect, is of a size suitable for contacting a packaged semiconductor device, such as in an LGA package.

Abstract: Methods, apparatus, and computer readable media for managing test result data generated by a semiconductor test system are described. Examples of the invention can relate to managing test result data generated by a semiconductor test system. In some examples, test result data is obtained from the semiconductor test system responsive to testing of a device under test (DUT). The test result data is processed for storage in a relational database using an interface generated in part based on design information of the DUT.

Abstract: In an integrated circuit assembly, know good die (KGD) are assembled on a substrate. Interconnect elements electrically connect pads on a die attached to the substrate to traces or other electrical conductors on the substrate or to pads on another die attached to the substrate. The substrate may have one or more openings, exposing pads of the die. The assembly may comprise one or more dice.

Abstract: A method and apparatus for testing a set of electronic devices can comprise placing electronic devices into a test station. A plurality of testers can provide test data to the test station. The test station can test the electronic devices using test data received from the plurality of testers. One of the testers can communication with another of the testers regarding the testing of the electronic devices. Probes can be used to contact the electronic devices, and one of the electronic devices can be contacted by more than one of the probes.

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract: Probe tips, methods for making probe tips, and method for using such probe trips are described. The probe tips can include a pedestal portion connected to a beam of a cantilever structure and a contact portion that can contact an electronic component that to be tested. The pedestal portion and contact portions can have a generally trapezoidal shape. The probe tips can also include a rectangular-shaped extension portion located between the base and contact portions. The probe tips can be made using a dual-etching process that creates the generally trapezoidal shape of the base and contact portions and the generally rectangular-shaped extension portion.

Abstract: A stiffener assembly for use with testing devices is provided herein. In some embodiments, a stiffener for use with testing devices includes an inner member; an outer member disposed in a predominantly spaced apart relation to the inner member; and a plurality of alignment mechanisms for orienting the inner and outer members with respect to each other, wherein the alignment mechanisms transfer forces applied to a lower surface of the inner member to the outer member and provide the predominant conductive heat transfer passageway between the inner and outer members.

Abstract: Improved lithographic type microelectronic spring structures and methods are disclosed, for providing improved tip height over a substrate, an improved elastic range, increased strength and reliability, and increased spring rates. The improved structures are suitable for being formed from a single integrated layer (or series of layers) deposited over a molded sacrificial substrate, thus avoiding multiple stepped lithographic layers and reducing manufacturing costs. In particular, lithographic structures that are contoured in the z-direction are disclosed, for achieving the foregoing improvements. For example, structures having a U-shaped cross-section, a V-shaped cross-section, and/or one or more ribs running along a length of the spring are disclosed. The present invention additionally provides a lithographic type spring contact that is corrugated to increase its effective length and elastic range and to reduce its footprint over a substrate, and springs which are contoured in plan view.

Abstract: Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (3) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (4) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (5) removing the contribution of rise time from measurement equipment; and (6) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time.

Abstract: Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Abstract: Embodiments of resilient contact elements and methods for fabricating and using same are provided herein. In one embodiment, a resilient contact element includes a lithographically formed resilient beam having a plurality of openings disposed laterally therethrough; and a tip disposed proximate a first end of the beam, the tip and the beam together configured to electrically probe a device to be tested.

Abstract: Methods and apparatus for testing devices using serially controlled resources have been described. Examples of the invention can relate to an apparatus for testing a device under test (DUT). In some examples, an apparatus can include an integrated circuit (IC) having a serialized input coupled to test circuits, the test circuits selectively communicating test signals with the DUT responsive to a test control signal on the serialized input.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.