Abstract: A probe card apparatus is configured to have a desired overall amount of compliance. The compliance of the probes of the probe card apparatus is determined, and an additional, predetermined amount of compliance is designed into the probe card apparatus so that the sum of the additional compliance and the compliance of the probes total the overall desired compliance of the probe card apparatus.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

Abstract: Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Abstract: Embodiments of methods and apparatus for aligning a probe card assembly in a test system are provided herein. In some embodiments, an apparatus for testing devices may include a probe card assembly having a plurality of probes, each probe having a tip for contacting a device to be tested, and having an identified set of one or more features that are preselected in accordance with selected criteria for aligning the probe card assembly within a prober after installation therein. In some embodiments, the identity of the identified set of one or more features may be communicated to the prober to facilitate a global alignment of the probe card assembly that minimizes an aggregate misalignment of all of the tips in the probe card assembly.

Abstract: An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals.

Abstract: Methods and apparatus for switching electrical signals are provided herein. In some embodiments a smart switch is provided, the smart switch may include a switch having a wipe capability; a monitor coupled to the switch for monitoring a performance characteristic thereof; and a controller configured to provide a stepped change in wipe applied by the switch between closing cycles thereof in response to the monitored performance characteristic. In some embodiments, an electronic device may be provided having a smart switch disposed therein.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: A stiffener structure, a wiring substrate, and a frame having a major surface disposed in a stack can be part of a probe card assembly. The wiring substrate can be disposed between the frame and the stiffener structure, and probe substrates can be coupled to the frame by one or more non-adjustably fixed coupling mechanisms. Each of the probe substrates can have probes that are electrically connected through the probe card assembly to an electrical interface on the wiring substrate to a test controller. The non-adjustably fixed coupling mechanisms can be simultaneously stiff in a first direction perpendicular to the major surface and flexible in a second direction generally parallel to the major surface.

Abstract: Systems and methods for providing a stack with a guard plane embedded in the stack are disclosed. An electrical apparatus can be made by forming a stack comprising an electrically conductive signal structure, an electrical guard structure, and an electrically insulating structure disposed between the signal structure and the guard structure. The signal structure, insulating structure, and guard structure can be aligned one with another in the stack.

Abstract: A stiffener assembly for use with testing devices is provided herein. In some embodiments, a stiffener for use with testing devices includes an inner member; an outer member disposed in a predominantly spaced apart relation to the inner member; and a plurality of alignment mechanisms for orienting the inner and outer members with respect to each other, wherein the alignment mechanisms transfer forces applied to a lower surface of the inner member to the outer member and provide the predominant conductive heat transfer passageway between the inner and outer members.

Abstract: A stiffener assembly for use with testing devices is provided herein. In some embodiments, a stiffener assembly for use with testing devices can be part of a probe card assembly that can include a stiffener assembly comprising an upper stiffener coupled to a plurality of lower stiffeners; and a substrate constrained between the upper stiffener and the plurality of lower stiffeners, the stiffener assembly restricting non-planar flex of the substrate while facilitating radial movement of the substrate with respect to the stiffener assembly.

Abstract: A probe for contacting and testing ICs on a semiconductor device includes a dielectric insulating material tip. The dielectric tip does not contaminate the surface being probed unlike metal probe tips. A contact scrub is further not required with signals being capacitively or inductively coupled from the probe tip to the IC. Testing can be performed during early fabrication steps of the wafer without the need for applying a metalization layer to the wafer to form bond pads. Testing can be performed by inductively coupling an AC signal to the probe tip, with coupling enhanced by including a magnetic material in the dielectric probe tip. Using an AC test signal enables testing of ICs without requiring separate power and ground connections.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: Methods and apparatus for providing a tester integrated circuit (IC) for testing a semiconductor device under test (DUT) are described. Examples of the invention can relate to an apparatus for testing a semiconductor device under test (DUT). In some examples, the apparatus can include an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits.

Abstract: Devices and methods for providing, making, and/or using an electronic apparatus having a wall structure adjacent a resilient contact structure on a substrate. The electronic apparatus can include a substrate and a plurality of electrically conductive resilient contact structures, which can extend from the substrate. A first of the contact structures can be part of an electrical path through the electronic apparatus. A first electrically conductive wall structure can also extend from the substrate, and the first wall structure can be disposed adjacent one of the contact structures. The first wall structure can be electrically connected to a return current path within the electronic apparatus for an alternating current signal or power on the first contact structure.

Abstract: An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.

Abstract: A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer system and communicated to the prospective customer. If feasible, additional software enables prospective customers to create verification packages according to their respective design specifications. These verification packages further consist of drawing files visually describing the final design and verification files confirming wafer bonding pad data. Verification packages are reviewed and forwarded to an applications engineer after customer approval. An interactive simulation of probe card performance is also provided.

Abstract: A test system can include contact elements for making electrical connections with test points of a DUT. The test system can also include a DC test resource and a signal router, which can be configured to switch a DC channel from the DC test resource between individual contact elements in a group of contact elements.

Abstract: A central test facility transmits wirelessly test data to a local test facility, which tests electronic devices using the test data. The local test facility transmits wirelessly response data generated by the electronic devices back to the central test facility, which analyzes the response data to determine which electronic devices passed the testing. The central test facility may provide the results of the testing to other entities, such as a design facility where the electronic devices were designed or a manufacturing facility where the electronic devices where manufactured. The central test facility may accept requests for test resources from any of a number of local test facilities, schedule test times corresponding to each test request, and at a scheduled test time, wirelessly transmits test data to a corresponding local test facility.