Patents Assigned to FormFactor
  • Patent number: 7732713
    Abstract: A robust mechanical structure is provided to prevent small foundation structures formed on a substrate from detaching from the substrate surface. The strengthened structure is formed by plating a foundation metal layer on a seed layer and then embedding the plated foundation structure in an adhesive polymer material, such as epoxy. Components, such as spring probes, can then be constructed on the plated foundation. The adhesive polymer material better assures the adhesion of the metal foundation structure to the substrate surface by counteracting forces applied to an element, such as a spring probe, attached to the plated foundation.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: June 8, 2010
    Assignee: FormFactor, Inc.
    Inventors: Gary W. Grube, Gaetan L. Mathieu, Benjamin N. Eldridge, Chadwick D. Sofield
  • Patent number: 7731546
    Abstract: A probing apparatus can include a plurality of contact probes, which can be of a type that is disposed along an axis. Each contact probe can include a contact portion, a base portion, and resilient portion. Multiple arms can form the resilient portion, which can be disposed between the contact portion and the base portion. The contact probes can be configured to twist when compressed. The probing apparatus can also include a substrate with through holes, and the contact probes can be inserted into the through holes. The resilient portion of each of the contact probes can bias the contact portion such that at least a portion of the contact portion extends out of a through hole.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: June 8, 2010
    Assignee: FormFactor, Inc.
    Inventors: Gary W. Grube, Gaetan L. Mathieu, Alec Madsen
  • Patent number: 7731503
    Abstract: A carbon nanotube contact structure can be used for making pressure connections to a DUT. The contact structure can be formed using a carbon nanotube film or with carbon nanotubes in solution. The carbon nanotube film can be grown in a trench in a sacrificial substrate in which a contact structure such as a beam or contact element is then formed by metal plating. The film can also be formed on a contact element and have metal posts dispersed therein to provide rigidity and elasticity. Contact structures or portions thereof can also be plated with a solution containing carbon nanotubes. The resulting contact structure can be tough, and can provide good electrical conductivity.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: June 8, 2010
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, John K. Gritters, Igor Y. Khandros, Rod Martens, Gaetan L. Mathieu
  • Patent number: 7732975
    Abstract: A gap-closing actuator includes a stator having one or more first electrodes, a mover having one or more second electrodes interposed among the first electrodes, and a biasing mechanism for applying a non-capacitive bias to the mover for urging the mover to move in a desired direction with respect to the stator. The non-capacitive bias is different from a capacitive force generated between the first and second electrodes when the gap-closing actuator is in operation.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: June 8, 2010
    Assignee: FormFactor, Inc.
    Inventors: Eric D. Hobbs, Gaetan L. Mathieu
  • Patent number: 7733106
    Abstract: An exemplary die carrier is disclosed. In some embodiments, the die carrier can hold a plurality of singulated dies while the dies are tested. The dies can be arranged on the carrier in a pattern that facilities testing the dies. The carrier can be configured to allow interchangeable interfaces to different testers to be attached to and detached from the carrier. The carrier can also be configured as a shipping container for the dies.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: June 8, 2010
    Assignee: FormFactor, Inc.
    Inventors: Thomas H. Dozier, II, Benjamin N. Eldridge, David S. Hsu, Igor Y. Khandros, Charles A. Miller
  • Patent number: 7729878
    Abstract: A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: June 1, 2010
    Assignee: FormFactor, Inc.
    Inventor: Gaetan L. Mathieu
  • Patent number: 7724004
    Abstract: A probing apparatus can comprise a substrate, conductive signal traces, probes, and electromagnetic shielding. The substrate can have a first surface and a second surface opposite the first surface, and the electrically conductive first signal traces can be disposed on the first surface of the first substrate. The probes can be attached to the first signal traces, and the electromagnetic shielding structures can be disposed about the signal traces.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: May 25, 2010
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Carl V. Reynolds, Takao Saeki, Yoichi Urakawa
  • Patent number: 7722371
    Abstract: An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 25, 2010
    Assignee: FormFactor, Inc.
    Inventor: Benjamin N. Eldridge
  • Patent number: 7714598
    Abstract: An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: May 11, 2010
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Thomas H. Dozier, II, Igor Y. Khandros, Gaetan L. Mathieu, William D. Smith
  • Patent number: 7714235
    Abstract: Microelectronic contact structures (260, 360, 460) are lithographically defined and fabricated by applying a masking layer (220, 320, 420) on a surface of a substrate (202, 302, 402) such as an electronic component, creating an opening (222, 322, 422) in the masking layer, depositing a conductive trace of a seed layer (250, 350, 450) onto the masking layer and into the openings, and building up a mass of conductive material on the conductive trace. The sidewalls of the opening can be sloped (tapered). The conductive trace can be patterned by depositing material through a stencil or shadow mask (240, 340, 440). A protruding feature (230, 430) may be disposed on the masking layer so that a tip end (264, 364, 464) of the contact structure acquires a topography. All of these elements can be constructed as a group to form a plurality of precisely positioned resilient contact structures.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: May 11, 2010
    Assignee: FormFactor, Inc.
    Inventors: David V. Pedersen, Igor Y. Khandros
  • Patent number: 7714603
    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: May 11, 2010
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Charles A. Miller
  • Patent number: 7701243
    Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: April 20, 2010
    Assignee: FormFactor, Inc.
    Inventors: Timothy E. Cooper, Benjamin N. Eldridge, Igor Y. Khandros, Rod Martens, Gaetan L. Mathieu
  • Patent number: 7699616
    Abstract: An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: April 20, 2010
    Assignee: FormFactor, Inc.
    Inventors: Charles A. Miller, Benjamin N. Eldridge
  • Patent number: 7694246
    Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: April 6, 2010
    Assignee: FormFactor, Inc.
    Inventors: Charles A. Miller, Timothy E. Cooper, Yoshikazu Hatsukano
  • Patent number: 7692433
    Abstract: A composite substrate for testing semiconductor devices is formed by selecting a plurality of substantially identical individual substrates, cutting a corner from at least some of the individual substrates in accordance with their position in a final array configuration, and then assembling the individual substrates into the final array configuration. The final array configuration of substrates with corners cut or sawed away conforms more closely to the surface area of a wafer being tested, and can easily fit within space limits of a test environment.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: April 6, 2010
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Roy J. Henson, Eric D. Hobbs, Peter B. Mathews, Makarand S. Shinde
  • Publication number: 20100079159
    Abstract: Methods and apparatus for providing a tester integrated circuit (IC) for testing a semiconductor device under test (DUT) are described. Examples of the invention can relate to an apparatus for testing a semiconductor device under test (DUT). In some examples, the apparatus can include an integrated circuit (IC) coupled to test probes configured to contact pads on the DUT, the IC including a plurality of dedicated test circuits coupled to programmable logic, the programmable logic responsive to programming data to form a tester for testing the DUT from at least one of the dedicated test circuits.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 1, 2010
    Applicant: FORMFACTOR, INC.
    Inventor: Todd Ryland Kemmerling
  • Patent number: 7688063
    Abstract: A thermal adjustment apparatus for adjusting one or more thermally induced movements of an electro-mechanical assembly includes: a compensating element expanding at a first rate different from a second rate at which the electro-mechanical assembly expands for generating a counteracting force in response to changes in temperature; and a coupling mechanism coupling the compensating element to the electro-mechanical assembly, and being adjustable to control an amount of the counteracting force applied to the electro-mechanical assembly as temperature changes.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 30, 2010
    Assignee: FormFactor, Inc.
    Inventors: Andrew W. McFarland, Kevin Youl Yasumura, Eric D. Hobbs, Keith J. Breinlinger
  • Patent number: 7688090
    Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 30, 2010
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, David V. Pedersen
  • Patent number: 7688085
    Abstract: In some embodiments of the invention, a probing apparatus can comprise a substrate, a spring structure attached to the substrate, and a plurality of resilient probes attached to the spring structure. Each probe can comprise a contact portion disposed to contact a device. The spring structure can provide a first source of compliance for each of the probes in response to forces on the contact portions of the probes, and each of the probes can individually provide second sources of compliance in response to the forces on the contact portions of the probes.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: March 30, 2010
    Assignee: FormFactor, Inc.
    Inventor: John K. Gritters
  • Patent number: 7683738
    Abstract: A transmission line includes a signal conductor and at least one varactor diode capacitively coupled to the signal conductor. The transmission line's signal path delay is a function of its shunt capacitance, and the varactor's capacitance forms a part of the transmission line's shunt capacitance. The transmission line's signal path delay is adjusted by adjusting a control voltage across the varactor diode thereby to adjust the varactor diode's capacitance.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 23, 2010
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller