Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: When a wireless communication device is receiving, a baseband circuit generates frequency domain LTE and WCDMA signals using a Fourier transform. The frequency domain WCDMA signal is then filtered with an RRC filter and converted back to the time domain using an inverse discrete Fourier transform. During transmission, the baseband circuit uses a Fourier transform to convert a time domain WCDMA signal to a frequency domain WCDMA signal. The frequency domain WCDMA signal is then filtered with an RRC filter and combined with a frequency domain LTE signal using an inverse Fourier Transform.

Abstract: Embodiments of switched-capacitor gain stage circuits and methods of their operation are provided. The circuit includes an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state. In the sampling state, the switches are configured so that a first charge component representing an input signal is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor. In the gain state, the switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor. In the output state, the switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node.

Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.

Abstract: A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.

Abstract: Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node.

Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Abstract: A lead frame used in semiconductor packaging has an outer dam bar and inner leads that extend away from the dam bar. The inner leads have distal ends and tips at the distal ends. Each inner lead has a coined area on a first major surface at the distal end and spaced from the tip. The coined area and the spacing of the coined area from the tip form a shoulder structure. The coined area is configured to receive one end of a bond wire that interconnects the inner lead with a wire bond pad of a semiconductor die. The shoulder structure creates a molding compound locking mechanism to reduce shear stress and delamination in the lead bonding area.

Abstract: A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.

Abstract: A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.

Abstract: An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35?) with gates (38, 38?) coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.

Abstract: A switching power converter converts an input DC voltage to an output DC voltage using a switch to selectively connect an input DC voltage energy source. A switching controller controls the switch. A pulse width modulation centering signal is generated by a spread spectrum clock signal generator. An error amplifier of the switching controller generates an analog error signal based on a switching voltage measured after the switching of the switching power converter, the output voltage of the switching power converter, the pulse width modulation centering signal and a reference. A pulse width modulated signal generator generates the pulse width modulation signal to control the switch of the switching power converter based on the pulse width modulation centering signal and the analog error signal.

Abstract: A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Abstract: In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time.

Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).

Abstract: Disclosed are example techniques for frame-based power management in a light emitting diode (LED) system having a plurality of LED strings. A voltage source provides an output voltage to drive the LED strings. An LED driver generates a frame timing reference representative of the frame rate or display timing of a series of image frames to be displayed via the LED system. An update reference is generated from the frame timing reference. The LED driver monitors one or more operating parameters of the LED system. In response to update triggers marked by the update reference, the LED driver adjusts the output voltage of the voltage source based on the status of each of the one or more monitored operating parameters (either from the previous update period or determined in response to the update trigger), thereby synchronizing the updating of the output voltage to the frame rate (or a virtual approximation of the frame rate) of the video being displayed.

Abstract: A method and a communication device for processing ATM cells. The communication device includes an input interface adapted to receive an ATM cell that is associated with a PHY value and includes a pair of VCI and VPI fields. The communication device is characterized by comprising a search unit, adapted to search, within a group of memory entries that belong to a memory unit, for a pair of VCI and VPI fields that have values that match the values of the VCI and VPI fields of the received ATM cell, if the received VCI field and VPI fields belong to a first predefined group of VCI and VPI fields. The communication device further includes a processor, connected to the search unit, wherein the processor is adapted to determine a channel identifier of the received ATM cell in response to a result of the search and in response to a PHY value associated with the received ATM cell.

Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.