Abstract: A power semiconductor device comprising an array of cells distributed over a surface of a substrate, the source regions of the individual cells of the array comprising a plurality of source region branches each extending laterally outwards towards at least one source region branch of an adjacent cell and presenting juxtaposed ends, the base regions of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches to form a single base region surrounding the source regions of the individual cells of the array in the substrate. The junctions between the merged base region and the drain region are solely concave laterally and define rounded current conduction path areas for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions to the drain electrode.

Abstract: A decoder comprising a decoding element arranged to operate in a first mode for decoding a turbo encoded data stream and in a second mode for decoding a viterbi encoded data stream, wherein the decoding element is responsive to a first control signal for switching from the first mode to the second mode during decoding of a turbo code block and responsive to a second control signal for switching from the second mode to the first mode to allow continued decoding of the turbo code block.

Abstract: A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor.

Abstract: A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier.

Abstract: An H-bridge drive circuit for reducing switching noises while preventing shoot-through current from flowing in the H-bridge circuit. The H-bridge drive circuit includes an H-bridge circuit for driving a load with a first power supply and a lower voltage second power supply. The H-bridge circuit includes first to fourth transistors. The first and third transistors are connected to the first power supply. The second transistor is connected between the first transistor and the second power supply, and the fourth transistor is connected between the third transistor and the second power supply. The load is connected to a node between the first and the second transistors and a node between the third and the fourth transistors. A control circuit switches the activation and inactivation of the first to fourth transistors so as to maintain at least either one of the second and fourth transistor in an activated state.

Abstract: A method is for packaging a first device having a first major surface and a second major surface. An encapsulant is formed over a second major surface of the first device and around sides of the first device. This leaves the first major surface of the first device exposed. A first dielectric layer is formed over the first major surface of the first device. a side contact interface is formed having at least a portion over the first dielectric layer. The encapsulant is cut to form a plurality of sides of encapsulant. A portion of the encapsulant is removed along a first side of the plurality of sides to expose a portion of the side contact interface along the first side of the plurality of sides.

Abstract: In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Abstract: An assembly for producing partially packaged semiconductor devices is provided. In one embodiment, the assembly includes a magnetic plate; a flexible substrate disposed adjacent the magnetic plate and having two surfaces; a nonstick coating disposed on one surface of the flexible substrate thereby exposing a nonstick surface; and a tape layer having two surfaces. The tape layer is adhesively attached to the nonstick surface to expose a surface of the tape layer. A frame is disposed on the exposed surface of the tape layer, and a plurality of integrated circuit (IC) die is positioned within the frame and supported by the tape layer. A panel is formed within the frame that at least partially surrounds the plurality of IC die and that contacts the tape layer.

Abstract: A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A method device and a method. The method includes fetching an instruction, decoding an instruction that includes an instruction type field, a first variable field, a second variable field, a result field and a constant field; selecting an operation out of addition operation, a subtraction operation and another type of operation, in response to the content of the instruction type field; determining, in response to the value of the constant field, whether the result of the selected operation is responsive to the first and second variables or is responsive to the first variable, the second variable and the constant; and executing the selected operation, during a single instruction execution cycle, to provide the result.

Abstract: A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit.

Abstract: Methods are provided for forming Quad Flat No-Lead (QFN) packages. An embodiment includes disposing an active side of a semiconductor chip on a plurality of leads, coupling a plurality of wire bonds to the active side of the semiconductor chip, coupling the plurality of wire bonds to the plurality of leads in a space between the active side and the plurality of leads, and encasing the semiconductor chip, at least a portion of each of the plurality of leads, and the plurality of wire bonds in a mold material to define a mounting side of the QFN package. The mounting side has a perimeter, the plurality of leads are oriented on and exposed on the mounting side within the perimeter, and the plurality of wire bonds are oriented between the active side and the mounting side within the mold material.

Abstract: An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.

Abstract: An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die.

Abstract: A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality of selectable temperature independent current sources for generating a temperature independent current, and a summer coupled to the temperature dependent current generator and the temperature independent current generator for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier. A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

Abstract: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region (63) defined in said fin and in said horizontal region.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.