Patents Assigned to Freescale Semiconductor
  • System and method for equalizing an incoming signal
    Publication number: 20090060022
    Abstract: An equalizer is provided, comprising: a feedback combiner to combine an input signal and a feedback signal to produce a first signal; a delay line to delay the first signal to produce a second signal; a feed-forward combiner to combine the second signal and a feed-forward signal to produce an output signal; an interim decision circuit to extract a sign bit from the first signal; N feedback scaling elements to generate N scaled feedback signals; M feed-forward scaling elements to generate M scaled feed forward signals; a feedback circuit to pass the N scaled feedback signals through feedback delay elements and feedback summing elements to generate the feedback signal in response to the sign bit; and a feed forward circuit to pass the M scaled feed forward signals through feed-forward delay elements and feed-forward summing elements to generate the feed-forward signal in response to the sign bit.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kaushal K. Dhar, Timothy R. Miller
  • METHOD OF PACKAGING AN INTEGRATED CIRCUIT DIE
    Publication number: 20090061564
    Abstract: A structure (40) for holding an integrated circuit die (38) during packaging includes a support substrate (42), a release film (44) attached to the substrate (42), and a swelling agent (60). A method (34) of packaging the die (38) includes placing the die (38) on the substrate (42) with its active surface (52) and bond pads (54) in contact with the film (44). The agent (60) is applied over an adhesive coating (50) of the film (44). The agent (60) causes the adhesive (50) to swell into contact with the bond pads (54) and/or to form fillets (64) of adhesive (50) about the die (38). The die (38) is encapsulated in a molding material (72) and released from the substrate (42) as a panel (74) of dies (38). Swelling of the adhesive (50) about the bond pads (54) prevents the molding material (72) from bleeding onto the bond pads (54).
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: William H. Lytle, Owen R. Fay, Jianwen Xu
  • METHODS AND STRUCTURES FOR AN INTEGRATED TWO-AXIS MAGNETIC FIELD SENSOR
    Publication number: 20090059444
    Abstract: A two-axis, single-chip external magnetic field sensor incorporates tunneling magneto-resistance (TMR) technology. In one embodiment, an integrated device includes at least two sensor elements having pinned layers with orientation situated at a known angle (e.g., 90 degrees) with respect to each other. In the presence of a magnetic field, the information from the multiple sensor elements can be processed (e.g., using a conventional bridge configuration) to determine the orientation of the integrated sensor with respect to the external field. In order to achieve an integrated sensor with multiple pinned layer orientations, a novel processing method utilizes antiferromagnetic pinning layers different materials with different blocking temperatures (e.g., PtMn and IrMn).
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Phillip Glenn Mather, Jijun Sun, Young Sir Chung
  • Universal serial bus transmitter
    Patent number: 7500033
    Abstract: A Universal Serial Bus transmitter comprising a USBTXP input and a USBTXM input for receiving respective data signals, and a USBP driver and a USBM driver for applying the respective data signals to USBP and USBM wires respectively. The transmitter comprises a transmit signal generator responsive to an asserting edge of a signal at one of the USBP and USBM inputs to define a leading edge of a transmit signal (USBTXIP) and to a corresponding de-asserting edge of a signal at the other of the USBP and USBM inputs to define the subsequent trailing edge of said transmit signal (USBTXIP). Even if the duty cycles of the input signals USBTXP and USBTXM are substantially different from 50%, this does not cause unacceptable jitter of successive crossover points nor cause the crossover point voltage level to be outside the USB tolerance, centred on 50% of the voltage swings of the USBP and USBM signals.
    Type: Grant
    Filed: February 6, 2005
    Date of Patent: March 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vincent Teil, Philippe Debosque, Cor H. Voorwinden
  • Apparatus and method for time ordering events in a system having multiple time domains
    Patent number: 7500152
    Abstract: A system and method time orders events that occur in various portions of the system (10) where different time domains (12, 22, 32) exist. Timestamping circuitry (e.g. 40) is provided in each of a plurality of functional circuits or modules (14, 24, 34). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module (70) is coupled to each of the plurality of functional circuits (14, 24, 34). The interface module (70) provides control information to the plurality of functional circuits (14, 24, 34) to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module (70) provides a timestamping message from one, several or all time domains at a common interface port (90).
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: March 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Richard G. Collins, Michael D. Fitzsimmons, Jason T. Nearing
  • Method for sharing bandwidth using reduced duty cycle signals
    Patent number: 7499442
    Abstract: A method is provided for transmitting data. A first device (121) generates a first signal (320) having a first duty cycle, comprising a first gated-on portion (323) and a first gated-off portion (363) in a time slot (260); and a second device (125) generates a second signal (330) having second duty cycle, comprising a second gated-on portion (333) and a second gated-off portion (363) in the same time slot (260). The first gated-on portion (323) is generated during a first segment of the time slot (260) and the first gated-off portion (363) is generated during a second segment of the time slot (260), while the second gated-on portion (333) is generated during the second segment and the second gated-off portion (363) is generated during the first segment. The first and second duty cycles are individually below 100%, and the sum of the first and second duty cycles is below 100%.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 3, 2009
    Assignee: Freescale semiconductor, Inc.
    Inventors: Matthew L. Welborn, William M. Shvodian
  • System and method for monitoring clock signal in an integrated circuit
    Patent number: 7498848
    Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: March 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjay Kumar Wadhwa, Amit Kumar Srivastava
  • Polishing pad, a polishing apparatus, and a process for using the polishing pad
    Patent number: 7497763
    Abstract: A polishing pad can include a first layer and a second layer. The first layer can have a first polishing surface and a first opening. The second layer can have an attaching surface and a second opening substantially contiguous with the first opening. The polishing pad can further include, a pad window lying within the first opening. The pad window can include a second polishing surface. When the pad would be attached to a platen, the first and second polishing surfaces can lie along a same plane, and an opposing surface of the pad window can abut an exterior surface of a platen window. In another aspect, a polishing apparatus can include an exterior surface of a platen window abutting the polishing pad. In still another aspect, a process of polishing can include polishing a workpiece such that the pad window contacts the workpiece and the platen window simultaneously.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: March 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian E. Bottema, Stephen F. Abraham, Alex P. Pamatat
  • Electronic fuse for overcurrent protection
    Patent number: 7498864
    Abstract: Current is provided from a first node coupled to an output of a power supply to a second node coupled to a voltage supply input of an electronic device under test via a transistor having a first current-carrying electrode coupled to the first node and a second current-carrying electrode coupled to the second node. A first voltage is determined based on a voltage difference between the first node and the second node and a second voltage is determined based on a comparison of the first voltage to a voltage of the second node. The transistor is selectively disabled based on the second voltage.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: March 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas R. Grover
  • Dynamic module output device and method thereof
    Patent number: 7499342
    Abstract: A dynamic module output device and methods thereof are disclosed. The dynamic module output device is connected to a dynamic module. The dynamic module output device provides the output of the dynamic module via two pathways. The first pathway is a direct output from the dynamic module. The second pathway includes a latch that stores the output of the dynamic module. The two output pathways are connected to a logic gate connected to downstream circuitry. Accordingly, data is provided to downstream circuitry rapidly via the first pathway, while being latched to allow the data to be available to the downstream circuitry after the evaluation phase. Such a parallel latching configuration provides enhanced efficiency in transfer and processing of information, especially in conjunction with utilization of precharge and evaluation phases.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: March 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Maciej Bajkowski, Ravindraraj Ramaraju, Andrew Russell
  • DIGITAL AUDIO AMPLIFIERS, ELECTRONIC SYSTEMS, AND METHODS
    Publication number: 20090051423
    Abstract: An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage.
    Type: Application
    Filed: August 25, 2007
    Publication date: February 26, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gerald P. Miaille, Julian Aschieri, Zhou Zhixu
  • METHOD AND APPARATUS FOR ENHANCED DATA RATE ADAPTATION AND LOWER POWER CONTROL IN A WLAN SEMICONDUCTOR CHIP
    Publication number: 20090052426
    Abstract: A method of optimising the operation of a WLAN device which is used in the transmission and reception of a service over a medium, the WLAN device comprising a WLAN chip set and power amplifier, the method comprising the steps of: determining a the value of a collision avoidance metric of the chip set at a specific time; predicting the available bandwidth of the WLAN from the value of the metric; determining the current data rate of the WLAN based on predicted available bandwidth and the type of service; and selecting a power amplifier bias voltage that is the minimum permitted for the determined current data rate to reduce the power consumption of the WLAN device.
    Type: Application
    Filed: March 15, 2006
    Publication date: February 26, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Eric Perraud
  • RF AMPLIFIER WITH STACKED TRANSISTORS, TRANSMITTING DEVICE, AND METHOD THEREFOR
    Publication number: 20090051435
    Abstract: An RF transmitting device (10) includes an RF amplifier (22) formed having components formed on a common semiconductor substrate (14). RF amplifier (22) includes MOS transistors (42) and (44) and an RF choke (46) stacked between a ground node (32) and a Vdd node (36). Transistors (42) and (44) are directly connected together and are biased by a control terminal bias network (58) so that the voltages appearing across their conduction terminals are about equal. Control terminals (56) and (62) of transistors (42) and (44) are driven by in-phase versions of an RF input signal (20).
    Type: Application
    Filed: August 20, 2007
    Publication date: February 26, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James R. Griffiths, David M. Gonzalez
  • PVT variation detection and compensation circuit
    Patent number: 7495465
    Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Qadeer A. Khan, Sanjay K Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
  • Low-noise amplifier
    Patent number: 7495515
    Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jason H. Branch, Lawrence E. Connell, Patrick L. Rakers, Poojan A. Wagh
  • Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
    Patent number: 7494856
    Abstract: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Ted R. White, Bich-Yen Nguyen
  • Semiconductor optical devices and method for forming
    Patent number: 7494832
    Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Voon-Yew Thean
  • Circuitry for latching
    Patent number: 7495493
    Abstract: Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding time (t(HL) and t(HH)) of the input signal with reference to the control signal is independent of the second edge of the control signal, and the output signal goes to a predetermined state in response to the second edge of the control signal. In one embodiment, the control signal may be a clock. The circuitry for latching may be used with static circuits and/or with dynamic circuits.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ravindraraj Ramaraju
  • Method for forming reinforced interconnects on a substrate
    Patent number: 7494924
    Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hei Ming Shiu, On Lok Chau, Gor Amie Lai, Heng Keong Yip, Thoon Khin Chang, Lan Chu Tan
  • Extending battery life in communication devices having a plurality of receivers
    Patent number: 7496060
    Abstract: A method (300) of extending battery life in a communication device having a plurality of receivers includes receiving information with a primary receiver that is configured to operate on a first network (303) and controlling a secondary receiver that is configured to operate on a second network that is independent from the first network in accordance with the information obtained with the primary receiver. A corresponding communication device (201) includes: a primary receiver (221) configured to operate on a first network (203); a secondary receiver (227, 233) configured and arranged to operate as a short range receiver with an access point (205, 207) that is independent of the first network; and a controller (225, 231, 237) that is configured to control the secondary receiver in accordance with information obtained from the primary receiver.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: February 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dalier J. Ramirez, James David Hughes, Ronald R. Rockwell