Patents Assigned to Freescale Semiconductor
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Patent number: 9071248Abstract: A circuit having an active mode and a sleep mode includes a power transistor, an amplifier, and a protection circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit for coupling to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode. The amplifier has an output coupled to the control electrode of the power transistor that provides an active output during the active mode. The protection circuit detects the leakage current and prevents the leakage current from developing a voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor.Type: GrantFiled: March 3, 2010Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Thierry Sicard, Laurent Guillot
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Patent number: 9070669Abstract: Methods of manufacturing a flat-pack no-lead microelectronic package (2100) coat exposed base metal at a cut end of a lead frame of the package with solder (1001). One method coats the exposed base metal with solder when the package is in a strip (200, 300). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end (504) on the package facilitates formation of a solder fillet during mounting of the package.Type: GrantFiled: November 9, 2012Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Dwight L. Daniels, Alan J. Magnus, Pamela A. O'Brien
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Patent number: 9070683Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.Type: GrantFiled: June 20, 2013Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jason R. Fender, Ngai Ming Lau
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Patent number: 9070653Abstract: A microelectronic assembly (100) and a microelectronic device (4100) include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.Type: GrantFiled: January 15, 2013Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Tab A. Stephens, Michael B. McShane, Perry H. Pelley
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Patent number: 9069896Abstract: During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.Type: GrantFiled: August 29, 2012Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jeffrey W. Scott, William C. Moyer
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Patent number: 9069042Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.Type: GrantFiled: November 5, 2013Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Rajesh Raina, Magdy S. Abadir, Darrell L. Carder
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Publication number: 20150177755Abstract: The present invention pertains to a linear power regulator device, comprising an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output, wherein the linear power regulator device comprises an external connection connectable or connected to an external pass device; and wherein the driver device is arranged to drive an external pass device via the driver output and the external connection. The invention also pertains to a corresponding electronic device.Type: ApplicationFiled: July 19, 2012Publication date: June 25, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Alexandre Pujol, Mohammed Mansri, Thierry Robin
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Publication number: 20150179566Abstract: A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Darrell G. Hill, Marcel N. Tutt
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Publication number: 20150177976Abstract: A method of scrolling a data set stored in a memory across a screen is described. The method comprises presenting a user interface widget on the screen. The user interface widget comprises one or more linear scroll bars and a rotation-sensitive scroll area. The method further comprises receiving one or more user inputs to the user interface widget, determining at least a scroll speed, a scroll direction and a scroll resolution from the one or more user inputs to obtain a scroll control signal, and scrolling the data set across the screen in accordance with the scroll control signal. A computer program product comprising instructions for causing a processor system to perform a method of scrolling a data set stored in a memory across a screen is described. A user interface widget is described. A device comprising a processor arranged to perform such method is described.Type: ApplicationFiled: August 8, 2012Publication date: June 25, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Razvan Ionescu, Radu-Marian Ivan, Ionut-Valentin Vicovan
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Publication number: 20150180475Abstract: An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.Type: ApplicationFiled: July 6, 2012Publication date: June 25, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Michael Priel, Dan Kuzmin, Sergey Sofer
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Patent number: 9065450Abstract: An integrated circuit device comprises tuning signal circuitry for generating a tuning signal for calibrating a voltage controlled oscillator (VCO). The tuning signal circuitry is arranged to receive a target voltage signal that is representative of a target voltage across at least one passive element within a resonant tank circuit of a VCO that is being calibrated, generate a VCO simulation signal representative of an average voltage difference across at least one active component of the VCO that is being calibrated, and output a tuning signal based at least partly on the received target voltage signal and the generated VCO simulation signal.Type: GrantFiled: June 29, 2010Date of Patent: June 23, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Lionel Geynet, Jean-Stephane Vigier
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Patent number: 9065475Abstract: A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analog sine and cosine waveforms indicative of fine position data and binary counterparts of the analog sine and cosine waveforms (Phase_A and Phase_B) indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analog sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analog sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.Type: GrantFiled: June 1, 2006Date of Patent: June 23, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Martin Mienkina, Leos Chalupa
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Patent number: 9063805Abstract: A method for enabling access to functionality provided by resources outside of an operating system environment is provided. The method includes: receiving a call for functionality provided by resources outside of the operating system environment; and copying function parameters from within the received call to an area of memory accessible to the resources outside of the operating system environment that provide the called functionality.Type: GrantFiled: November 25, 2009Date of Patent: June 23, 2015Assignee: Freescale Semiconductor, Inc.Inventors: John Ralston, Andrea Acquaviva
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Patent number: 9064938Abstract: An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.Type: GrantFiled: May 30, 2013Date of Patent: June 23, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Melanie Etherton, Alexey Gilgur, James W. Miller, Jonathan M. Phillippe, Robert S. Ruth
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Patent number: 9061589Abstract: A display controller includes a controller input connectable to receive first image data representing a non-safety relevant part of an image to be displayed on a display and to receive second image data representing a safety relevant part of the image. A merging unit is connected to the controller input, for composing the image from the first image data and second image data. A controller output is connectable to the display, for outputting display data representing the image. An image monitor is connected to the controller output, for comparing a part of the image corresponding to the safety relevant part with an reference for the part.Type: GrantFiled: May 20, 2008Date of Patent: June 23, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Florian Bogenberger, Davor Bogavac
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Patent number: 9063747Abstract: In a processor, a decode unit identifies instructions needing a checkpoint and enables selected checkpoints. A register file unit includes a plurality of architectural registers. A first set of checkpoint registers correspond to a first checkpoint. Each checkpoint register corresponds to a corresponding architectural register. A first set of indicators correspond to the first set of checkpoint registers to indicate whether the corresponding architectural register has been modified or is intended to be modified prior to enabling of the first checkpoint. A second set of indicators correspond to the first set of checkpoint registers and indicate whether the corresponding architectural register has been modified or is intended to be modified after enabling the first checkpoint.Type: GrantFiled: April 28, 2011Date of Patent: June 23, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Thang M. Tran
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Publication number: 20150172220Abstract: An EtherCAT packet forwarding system with distributed clocking is provided. The system comprises a master device and a plurality of slaves. The master comprises a processing port and a forward port for being respectively coupled to the at least two Ethernet ports of the master device in a redundant ring topology. The slaves comprise an internal clock indicating a current time, and a slave memory comprising a processing timestamp variable, a forwarding timestamp variable, a temporary timestamp variable and a copy-direct bit.Type: ApplicationFiled: July 2, 2012Publication date: June 18, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Hezi Rahamim, Amir Yosha
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Patent number: 9058203Abstract: A distributed processor-based system comprises a plurality of communicating platforms, wherein a number of platforms in the distributed processor-based system comprise at least one compiler, the at least one compiler being operably coupled to data type translation logic and arranged to generate a memory layout for the respective platform. In response to an indication for a communication to occur between a first platform and a second platform the data type translation logic translates a memory layout using data type attributes for data to be transferred from the first platform to the second platform based on at least one platform-specific characteristic, such that the data does not require translating when received at the second platform.Type: GrantFiled: November 20, 2006Date of Patent: June 16, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Madalin Broscaru, Christian Caciuloiu
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Patent number: 9059008Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.Type: GrantFiled: October 19, 2012Date of Patent: June 16, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
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Patent number: 9059144Abstract: A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.Type: GrantFiled: February 23, 2012Date of Patent: June 16, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Leo M. Higgins, III, Burton J. Carpenter, Glenn G. Daves
