Patents Assigned to Fujian Jinhua Integrated Circuit Co., Ltd.
  • Patent number: 12224283
    Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: February 11, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Yu-Cheng Tung
  • Patent number: 12225715
    Abstract: A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and respectively extending along a first direction and arranged into an array, and a plurality of isolation structures disposed in the substrate between the active regions. The isolation structures respectively comprise an upper portion and a lower portion, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different. The semiconductor device further includes a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: February 11, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Patent number: 12219751
    Abstract: A semiconductor memory device includes a substrate and a capacitor. The capacitor is disposed on the substrate, and the capacitor includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer sequentially stacked from bottom to top and an aluminum-containing insulation layer. The aluminum-containing insulation layer includes aluminum titanium nitride or aluminum oxynitride, and is in direct contact with the capacitor dielectric layer and disposed between the bottom electrode layer and the top electrode layer. Therefore, the semiconductor memory device may effectively improve the leakage current.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: February 4, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Min-Teng Chen
  • Publication number: 20250038142
    Abstract: A semiconductor device includes a substrate, plugs and a storage node pad structure. The plugs are disposed on the substrate and include first plugs with a conductive material and second plugs with an insulating material. The storage node pad structure is disposed on the plugs and includes first extension pads and at least one second extension pad. The first extension pads have a predetermined first length in a first direction and are separated from each other and arranged as an array along the first direction, being in physical contact with one of the first plugs. The at least one second extension pad has a length greater than the predetermined first length and is in physical contact with at least one of the plugs.
    Type: Application
    Filed: December 7, 2023
    Publication date: January 30, 2025
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yifei Yan
  • Patent number: 12213303
    Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: January 28, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
  • Publication number: 20250031389
    Abstract: A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.
    Type: Application
    Filed: November 13, 2023
    Publication date: January 23, 2025
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Bingxing Wu, Jung-Hua Chen, Wei-Ming Hsiao, Yu-Cheng Tung, Qiangwei Xu
  • Patent number: 12200923
    Abstract: The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: January 14, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Publication number: 20250016982
    Abstract: A semiconductor structure includes a substrate, a first bottom electrode and a second bottom electrode disposed on the substrate, an upper supporting layer extending laterally between the first bottom electrode and the second bottom electrode and directly contacting the first bottom electrode and the second bottom electrode, a cavity between the upper sacrificial layer and the substrate, a capacitor dielectric layer covering along the first bottom electrode and the second bottom electrode, and a conductive material disposed on the capacitor dielectric layer. A portion of the first bottom electrode has a slope profile having a lower end not lower than a lower surface of the upper supporting layer.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Janbo Zhang
  • Patent number: 12191299
    Abstract: The present disclosure provides a method of fabricating a semiconductor device, which includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate and includes a first active area, a second active area disposed outside the first active area, and a third active area disposed outside the second active area. The shallow trench isolation is disposed in the substrate to surround the active structure. Through the second active area and the third active of the active structure, the structural stability of the semiconductor device may be enhanced to improve the stress around the semiconductor device, thereby preventing from structural collapse or deformation.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: January 7, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yifei Yan
  • Publication number: 20240427230
    Abstract: A method of forming a photomask includes: providing a target pattern; generating a first offset pattern according to the target pattern and a first offset value; generating a second offset pattern according to the first offset pattern and a second offset value; operating the first offset pattern and the second offset pattern with a Boolean operation to obtain a first assist feature; and outputting the target pattern and the first assist feature to form the photomask. The manufacturing time of the resulting photomask can be shortened and fidelity of patterns produced by the photomask can be improved so as to facilitate transfer of the target pattern to the semiconductor substrate precisely.
    Type: Application
    Filed: October 17, 2023
    Publication date: December 26, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Joey Xie
  • Publication number: 20240421184
    Abstract: In a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, conductive layer structures, plug structures, spacers and stop layers. The plug structures are disposed between two of the conductive layer structures in a second direction perpendicular to the first direction. The spacers are disposed between the conductive layer structures and the plug structures. The stop layers are disposed on the spacers between the conductive layer structures and the plug structures and has a bottommost surface disposed between a bottom surface of the conductive layer structures and a bottom surface of the spacers. The plug structures comprise at least one protrusion member extending from the bottommost surface toward the conductive layer structure and disposed between the stop layer and the substrate. Accordingly, contact area between the plug structures and the substrate can be increased.
    Type: Application
    Filed: November 22, 2023
    Publication date: December 19, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Yu-Cheng Tung, Hsi-Chih Li, Tsung-Yi Wu
  • Publication number: 20240422958
    Abstract: A semiconductor device which includes a substrate, storage node pads, a capacitor structure and a supporting structure, and a forming method thereof are disclosed. The substrate includes a cell region and a periphery region. The storage node pads are disposed on the substrate and located in the cell region. The capacitor structure is disposed on the storage node pads and includes bottom electrodes in contact with the storage node pads. The supporting structure is disposed on the storage node pads and interleaved among the bottom electrodes. The supporting structure includes a first supporting layer and a second supporting layer sequentially from bottom to top. The second supporting layer includes a first thickness and a second thickness, wherein the second thickness is greater than the first thickness, and the second supporting layer with the second thickness is disposed between the cell region and the periphery region to provide improved structural support.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 19, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Li-Wei Feng
  • Publication number: 20240412772
    Abstract: A memory structure includes a substrate, a first device layer disposed on the substrate, a plurality of memory regions in the first device layer, a plurality of word lines and bit lines in the first device layer to control memory cells of the memory regions, a second device layer disposed between the substrate and the first device layer, and first peripheral regions and second peripheral regions in the second device layer, wherein in a top view, the first peripheral regions and the second peripheral regions respectively partially overlap adjacent two of the memory regions.
    Type: Application
    Filed: October 4, 2023
    Publication date: December 12, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yifei Yan, Hui-Huang Chen, Chao-Wei Lin
  • Publication number: 20240405086
    Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, includes a substrate, a gate structure, a plug hole, a plug spacer, a metal silicide layer, and a plug. The gate structure is disposed on the substrate. The plug hole is disposed within a dielectric layer to partially extended into the substrate. The plug spacer is disposed on a sidewall of the plug hole to partially expose the substrate. The metal silicide layer is disposed at a bottom of the plug hole, wherein a portion of the substrate is sandwiched between the metal silicide layer and the plug spacer. The plug is disposed in the plug hole to physically contact the portion of the substrate. Accordingly, through forming the plug spacer to precisely define the forming location and the depth of the metal silicide layer, thereby achieving the function on improving the performance of the semiconductor device.
    Type: Application
    Filed: July 21, 2023
    Publication date: December 5, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chi-Ren Luo, Yifei Yan
  • Publication number: 20240397703
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a first stacked structure disposed in the semiconductor substrate, and a contact structure. The semiconductor substrate includes a fin-shaped structure. The first stacked structure is disposed straddling the fin-shaped structure, extends in a horizontal direction, and disposed in the cell region and the peripheral region. The first stacked structure includes an electrically conductive layer including a first portion in the cell region and a second portion in the peripheral region, a capping layer disposed on the electrically conductive layer, and a dielectric capping layer disposed on the capping layer and the electrically conductive layer. The dielectric capping layer contacts a top surface of the second portion.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Huixian LAI, Li-Wei Feng
  • Publication number: 20240395605
    Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Patent number: 12156399
    Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: November 26, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Huixian Lai, Yi-Wang Jhan
  • Publication number: 20240387395
    Abstract: A semiconductor device, a method of forming the same and a method of measuring the same are disclosed. The semiconductor device includes a substrate, a first dielectric layer, first alignment marks, a second dielectric layer and second alignment marks. The first dielectric layer is arranged on the substrate, the first alignment marks are arranged in the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second alignment marks are arranged in the second dielectric layer and spaced apart from each other, each having a stepped structure. The first and second alignment marks do not interfere with each other. A precisely positioned interconnection structure can thus be defined in the semiconductor device.
    Type: Application
    Filed: September 5, 2023
    Publication date: November 21, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: JIANPENG LAI, Rongxiang Zhong, Yue Liu, Chung-Ping Hsia
  • Patent number: 12150291
    Abstract: A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: November 19, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Yu-Cheng Tung
  • Patent number: 12147156
    Abstract: The present disclosure discloses a method of fabricating a semiconductor layout comprising the following steps. A layout is provided, and the layout includes a plurality of connection patterns. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. Accordingly, the quality of the photomask may be improved, and the photomask may therefore include more accurate patterns and contours. The present disclosure also provides a method of fabricating a semiconductor structure.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 19, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yifei Yan, Wenzhang Li