Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: A semiconductor structure is provided in the present invention, including a substrate with multiple recesses and active areas, multiple bit lines spaced apart in a first direction on the cell region and extending in a second direction perpendicular to the first direction, and the bit line is electrically connected to an active area in the substrate through the recess, and a dummy bit line at an outermost side of the multiple bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and the bit lines and the dummy bit line have the same composition and layer structures.

Abstract: A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Abstract: The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, includes a substrate, a plurality of gate structures, a plurality of isolation fins, at least one bit line, and a plug. The gate structures are disposed in the substrate, being parallel with each other along a first direction. The isolation fins are disposed on the substrate, parallel with each other and extending along the first direction, over each of the gate structures respectively. The bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The bit line includes a plurality of pins extending toward the substrate, being alternately arranged with the isolation fins along the second direction. The plug is disposed on the substrate, being alternately with the bit line in the first direction.

Abstract: The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

Abstract: A three-dimensional memory device includes a staircase structure comprising steps respectively comprising a conductive layers and a dielectric layer. A sidewall of the conductive layer is recessed from a sidewall of the dielectric layer to form a recess that exposes a portion of a bottom surface of the dielectric layer.

Abstract: A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, the stacked structure comprises a first support layer, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, a portion of a sidewall of the first support layer directly contacts a portion of a sidewall of the second support layer, and a capacitor structure located in the cell array region.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor memory device including a substrate, bit lines, contacts, a dielectric layer, storage node pads and a capacitor structure. The bit lines are disposed on the substrate and include a plurality of first bit lines and at least one second bit line. The contacts are disposed on the substrate and alternately and separately disposed with the bit lines. The dielectric layer is disposed over the contacts and bit lines. The storage node pads are disposed in the dielectric layer and respectively contact the contacts. The capacitor structure is disposed on the storage node pads and includes a plurality of first capacitors and at least one second capacitor located above at least one second bit line. Therefore, the semiconductor memory device can achieve more optimized device performance.

Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.