Patents Assigned to Fujian Jinhua Integrated Circuit Co., Ltd.
  • METHOD OF FABRICATING SEMICONDUCTOR MEMORY
    Publication number: 20220359527
    Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.
    Type: Application
    Filed: July 5, 2022
    Publication date: November 10, 2022
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Enping Cheng, Li-Wei Feng, Yu-Cheng Tung
  • Active region structure and the forming method thereof
    Publication number: 20220359534
    Abstract: The present invention provides an active region structure, the active region structure includes a plurality of sub-closed conductive patterns located on a substrate, the sub-closed conductive patterns are in contact with each other and form a larger closed pattern, a first boundary of the larger closed pattern extends along a horizontal direction, and a second boundary of the larger closed pattern extends along a vertical direction.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Gang-Yi Lin
  • Active region structure and the forming method thereof
    Patent number: 11482424
    Abstract: The invention discloses an active region structure and a manufacturing method thereof, which also comprises a edge portion around the active region, so that the stress generated by the shallow trench insulation layer in the peripheral area on the active region can be blocked, and the component unit in the peripheral edge area of the active region can be prevented from being damaged due to stress. In addition, the edge portion includes branches extending into the active region, and the branches extend in at least two different directions, which can compensate the uneven stress at the end between the active lines and avoid the damage of the component unit.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: October 25, 2022
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Gang-Yi Lin
  • MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    Publication number: 20220293721
    Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, the stacked structure comprises a first support layer, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, a portion of a sidewall of the first support layer directly contacts a portion of a sidewall of the second support layer, and a capacitor structure located in the cell array region.
    Type: Application
    Filed: May 29, 2022
    Publication date: September 15, 2022
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • SEMICONDUCTOR DEVICE
    Publication number: 20220271037
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
    Type: Application
    Filed: May 10, 2022
    Publication date: August 25, 2022
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
  • Semiconductor memory device having a second active region disposed at an outer side of a first active region
    Patent number: 11424247
    Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: August 23, 2022
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Enping Cheng, Li-Wei Feng, Yu-Cheng Tung
  • Semiconductor device and method for fabricating the same
    Patent number: 11411009
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 9, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wen-Fu Huang, Fu-Che Lee
  • Semiconductor device and method of forming the same
    Patent number: 11393826
    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 19, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
  • Manufacturing method of semiconductor device and semiconductor device
    Patent number: 11380754
    Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, and a capacitor structure located in the cell array region.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 5, 2022
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Memory device and method of fabricating same
    Patent number: 11374010
    Abstract: A memory device and a method of fabricating the memory device are disclosed, in which a plurality of contacts are formed on a substrate, and voids are formed in the contacts. The contacts are electrically isolated from one another by cutouts directly connecting with the voids. Insulating layers at least fill the cutouts. Since the cutouts are connected with the voids and the insulating layers fill at least the cutouts, the voids can be kept at least partially void. Thus, they can reduce parasitic capacitance between the contacts, prevent the degradation of data retention properties of the memory device, and overcome the problem of malfunctioning. Additionally, the need to avoid the formation of voids in the contacts by imposing strict requirements on the process for forming the contacts can be dispensed with, thus widening the process window for the formation of the contacts.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: June 28, 2022
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Qinfu Zhang
  • Buried word line of a dynamic random access memory and method for fabricating the same
    Patent number: 11367725
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 21, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • MEMORY DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20220139922
    Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.
    Type: Application
    Filed: August 17, 2021
    Publication date: May 5, 2022
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wang Jhan, Yu-Cheng Tung, Fu-Che Lee, Chien-Cheng Tsai, An-Chi Liu, Ming-Feng Kuo, Gang-Yi Lin, JUNYI ZHENG
  • BURIED WORD LINE OF A DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME
    Publication number: 20220130839
    Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
  • METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20220122988
    Abstract: A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ming Lu, Fu-Che Lee, Chien-Cheng Tsai, Chiu-Fang Hsu
  • SEMICONDUCTOR DEVICE
    Publication number: 20220122845
    Abstract: A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.
    Type: Application
    Filed: December 26, 2021
    Publication date: April 21, 2022
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20220122984
    Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.
    Type: Application
    Filed: August 9, 2021
    Publication date: April 21, 2022
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Cheng Tung, Huixian LAI, Yi-Wang Jhan
  • Memory device
    Patent number: 11289153
    Abstract: A memory device is disclosed, in which node contacts extend into a substrate, where they are come into electrical connection with active areas. This allows greater contact areas between the node contacts and the active areas and electrical connection of the node contacts with high ion concentration portions of the active areas. As a result, even when voids are formed in the node contacts, the node contacts can still possess desired connection performance. For node contacts allowed to contain voids, this enables them to be fabricated faster with lower difficulty, thus increasing manufacturing throughput of the memory device.
    Type: Grant
    Filed: June 20, 2021
    Date of Patent: March 29, 2022
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jianfang Wang, Peng Guo, Baoyu Li, Yuanbao Wang
  • Capacitor structure
    Patent number: 11289489
    Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 29, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Method for fabricating semiconductor device
    Patent number: 11271000
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a first oxide layer in the trench; forming a silicon layer on the first oxide layer; performing an oxidation process to transform the silicon layer into a second oxide layer; and planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 8, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Bo-Ruei Cheng, Li-Wei Feng
  • Buried word line of a dynamic random access memory and method for fabricating the same
    Patent number: 11251187
    Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 15, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng