Abstract: An image scanner-reader has an image read unit, and an employing control unit. The image read unit is used to read an original document and provide image data of the original document. The employing control unit is used to control the relative moving speed between the original document and the image read unit, and when an original document reading operation is suspended, the employing control unit controls the restart of the reading operation after decreasing the relative moving speed to a slow reading speed of the original document. Therefore, when the image data buffer becomes full enough to cause a suspension state, and the read operation is restarted after changing control conditions, so that the quantity of data transferred to the image data buffer is reduced. Namely, according to the present invention, the number of occurrences of the suspension state can be greatly reduced, and thereby the overal reading speed can be improved without increasing the data receiving speed of a host device.

Abstract: A contrast adjustment circuit for a liquid crystal display which is connected, when to be used, to an electronic apparatus such as a computer. The contrast adjustment circuit comprises an adjustment voltage supply circuit provided in an electronic apparatus, a reference voltage generation circuit provided in the liquid crystal display for generating a reference voltage substantially equal in absolute value to a contrast peak voltage of the liquid crystal display, and an operational amplifier for comparing the reference voltage and an adjustment voltage and supplying a voltage difference between the reference voltage and the adjustment voltage to a driving voltage input terminal of the liquid crystal display.

Abstract: A method and a system for driving an electro-luminescence display panel of a matrix type has a compensation pulse applied to all the cells prior to or in the front of a pedestal pulse on every frame cycle. The level of the compensation pulse is higher than the pedestal pulse but low enough not to light the cells by itself. The duration of the compensation pulse is long enough to saturate charge polarization in the EL material of the cell, as a dielectric, at the applied voltage. Therefore, brightness of the lighted cell is kept constant regardless of the number of lighted cells on the same data electrode. Each of two power-receiving terminals of push-pull scan drivers is connected to a pulse generator respectively. One of the two power-receiving terminals may be floated from the pulse generator while data pulse is applied to the data electrodes.

Abstract: A high-density laminated connector having a plurality of rigid dielectric layers laminated together is described. The rigid construction of the connector permits precise dimensions of the connector and, thus, accurate attachment of adjacent interconnect substrates. The dielectric layers include traces which have contact pads or bumps formed at the surfaces of the connector for connection to the traces of one or more adjacent interconnect substrates. The contact pads may comprise soft gold, solder, or various elastomeric materials. The use of soft gold contacts enables the connector to be easily removed from an adjacent interconnect substrate. In other embodiments, the rigid dielectric layers may comprise recesses where the contact pads are placed. This ensures physical alignment of the interconnect substrate and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction.

Abstract: A semiconductor storage device includes a plurality of memory cells, a selecting circuit for selecting, in accordance with address information supplied from an external unit, a memory cell from among the plurality of memory cells, there being a case where a memory cell identified by the address information supplied from the external unit is not present in the plurality of memory cells, a data line to which the plurality of memory cells are coupled, data read out from the selected memory cell being transmitted through the data line, the data line being able to be in a floating state when a memory cell identified by address information is not present in the plurality of memory cells, an amplifier for amplifying the data transmitted through the data line, a latching circuit for latching a potential level of data which has been supplied to the data line, and a control circuit for controlling the latching circuit so that the latching circuit is inactive in a predetermined period including a time at which the data

Abstract: The setting and phase adjusting apparatus for synchronous multiplex communications is provided which adjusts phase differences of main signals caused between a plurality of synchronous multiplexing sections and a line setting section during line setting, in which to reduce the scale of circuitry of the line setting section in a transmission device for carrying out multiplexing and line setting on large-capacity signals, a plurality of pointer modifiers are arranged on a shelf on which the line setting section is arranged. The pointer modifiers connect the line setting section to the respective synchronous multiplexing sections. The pointer modifiers are supplied with multiplexed signals of respective signal series whose data head positions are shifted from one another. The head positions of these signals are synchronized with a timing signal from a timing generator by the pointer modifiers. Line switching is then effected by time switches and a space switch.

Abstract: A method of producing a semiconductor memory cell. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads and two word lines respectively coupled to gate electrodes of the transfer transistors.

Abstract: In an output circuit for driving a load connected to an output terminal in accordance with an input signal input to an input terminal, the output circuit connects to the input and output terminals, a first output buffer which operates when activated; connects in parallel to the first output buffer, a second output buffer which, when activated, operates with driving ability higher than the first output buffer; and activates the second output buffer for a predetermined period when the input signal is input and, after the period, activates the first output buffer.

Abstract: An SDH (synchronous digital hierarchy) 2-fiber ring network optical multiplexing device, which, in order to increase the amount of usable bandwidth when the network is operating normally by selectively limiting the number of protection channels when a communications fault is detected, has opto-electrical converters and electro-optical converters for the purpose of sending and receiving signals on each optical transmission path in two directions, a channel operating section which perform operations on the required channel for the transmitted and received signals, a transmitting/receiving control section which performs transmitting/receiving control of the required channel signals with respect to channel operating section, and an input/output interface section which interfaces signals received from and transmitted to the outside, wherein the transmitting/receiving control section allocates different numbers of channels so as to limit the number of protection channels with respect to the number of working channe

Abstract: A cache uses A bits of an offset portion which are not subjected to the address translation of the logical address and B bits of the portion other than the offset portion, which are subjected to an address translation. It has an address monitor portion having a tag portion corresponding to the tag portion of the CPU using only A bits of the offset portion of the set address which are used as the set address in the cache and having a 2.sup.B .times.N-way set associative structure and a portion for making said tag portion of the cache correspond to said tag portion of the address monitor portion, thereby performing management of N address stored in the tag portion of the address monitor portion and transmitting the result of the management of the address to the cache and for invalidating the corresponding recording portion of the tag in the cache.

Abstract: A graphic data processor employs a CAD system having an input part, a design model managing part and a display part. The design model managing part includes a model area creating unit for securing a model area and formatting the model area into function figures, layers, figure groups, and figures, a model accessing unit for accessing the model area and an external file, a model data retrieving unit for hierarchically retrieving data from the model area and a model updating unit for creating model information and correcting figure information.

Abstract: An electron beam apparatus comprises, inside of an objective lens for focussing a primary electron beam e1 and irradiating it on a sample surface, a secondary electron energy analyzer having a retarding mesh electrode for analyzing the energy of a secondary electron e2 emitted from a point on the sample surface at which the primary electron beam e1 is irradiated. The secondary electron energy analyzer comprises a collimation unit for forming one or more electrostatic lenses by a nonuniform electrical field distribution and for having an electrostatic lens collimate the trajectory of a secondary electron e2 for its injection into a retarding grids (mesh electrode). The collimation unit comprises at least three cylindrical electrodes positioned between the sample surface and the retarding grid (mesh electrode) and numbered first, second and third from the one closest to the sample surface.

Abstract: A system bus control system for a system has a plurality of first modules and at least one second module. The first and second modules are connected together via a system bus which is controlled by an arbiter receiving requests to use the system bus from the first and second modules. Each of the first modules includes a lock control signal supervising unit, a lock control signal outputting unit, a command outputting unit and a response receiving unit. Each of the second modules includes a lock control signal supervising unit, a source module information storing unit, a command receiving unit and a response outputting unit. The lock control is controlled by the first and second modules rather than the arbiter, which permits one of the first and second modules to use the system bus if the system bus is idle.

Abstract: A semiconductor integrated circuit device includes a memory storing a microprogram used for controlling a desired function, a generator for generating an internal microprogram activating signal. A switching part selects either one of an external microprogram activating signal generated by an external device and the internal microprogram activating signal generated by the generator based on a first signal supplied from outside of the semiconductor integrated circuit device, thereby outputting a selected microprogram activating signal. A microaddress generator generates a microaddress of the microprogram stored in the memory. The microaddress generator is activated by the selected microprogram activating signal.

Abstract: Disclosed is a heat roller fixing apparatus for performing a thermal fixation onto a sheet by rotating a heat roller. This heat roller fixing apparatus comprises a heat roller including a roller body and a plurality of heating members provided in the roller body and a pressurizing member provided in a face-to-face relationship with the heat roller. This heat roller fixing apparatus has a rotation mechanism for rotating the plurality of heating members along an inner periphery of the roller body and a control unit for drive-controlling the rotation mechanism during a standby status for driving the heating members without rotating the roller body. An unevenness in preheating on the surface of the roller body of the heat roller is thereby prevented.

Abstract: An apparatus for verifying service user's information consists of a switch system for setting a call between one terminal and the other terminal and a data memory connected to this switch system. This data memory stores information indicating the number of a service user on which a charge previously applied by a subscriber is imposed and information on a validity of this service user's information. The switch system includes a checking section. The checking section checks at first effects, when the subscriber requests setting of a call to be charged for a talk on the basis of the above-mentioned information from one terminal, a formal check of the service user's information sent with the request by the subscriber. If this formal check is passed, the checking section requests the data memory for a collation as to whether or not the service user's information is valid.

Abstract: A method of producing a memory cell on a semiconductor substrate. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads, and two memory capacitors. A field insulator layer is formed on the semiconductor substrate. A gate insulator layer is formed above the field insulator layer. A gate electrode of a driver transistor is produced by forming a first conductor layer above the gate insulator layer. Impurity regions are formed in the semiconductor substrate using the field insulator layer and the first conductor layer as masks. A first insulator layer is then formed. Source, drain and channel regions of a thin film transistor load are produced by forming a second conductor layer and injecting impurities into the second conductor layer. A second insulator layer is formed above the second conductor layer. A contact hole is formed to extend from the second insulator layer, through the second conductor layer, and to the first conductor layer.

Abstract: A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included.

Abstract: A paper feeder installed in a recording apparatus is capable of selectively performing two-sided recording on sheet paper and includes a paper supply passageway for supplying the sheet paper to a recording unit of the recording apparatus, a paper eject passageway for ejecting from the recording unit the sheet paper on which recording has been performed and a paper bypass passageway which extends between the paper supply passageway and the paper eject passageway. A paper switching unit is provided at a branched portion between the paper eject passageway and the paper bypass passageway. Paper feed rollers can be driven in forward and reverse directions so that the sheet paper can be fed along the paper eject passageway in two directions. The paper feed rollers are arranged on the downstream side of the paper switching unit in the ejection direction of the sheet paper.

Abstract: A reticle and a method of fabricating the same for projecting a fine pattern on an object surface comprises: a transparent substrate; a first type phase-shifter selectively patterned and deposited on the substrate producing a phase difference between the light passing therethrough and the light passing through the other areas without phase-shifter; and a second type phase-shifter selectively patterned and forming a groove in the substrate producing a phase difference between the light passing therethrough and the light passing through the other areas without phase-shifter. The reticle may include a patterned shield layer which interrupts transmission of light, and the phase difference of the first and second type phase-shifters is many times selected substantially equal to a half wavelength of light. Another type of a reticle comprises: a transparent substrate; a phase-shifter of a first groove; and another phase-shifter of a second deeper groove formed in the first groove.