Patents Assigned to Fujitsu Semiconductor Limited
  • Patent number: 10840130
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Publication number: 20200335148
    Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Keizo Morita
  • Patent number: 10803910
    Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: October 13, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Keizo Morita
  • Patent number: 10740225
    Abstract: A radio communication processor receives first received data including first write data, a first address within a first area of a nonvolatile memory, and error detection information or second received data including second write data whose data amount is larger than a data amount of the first write data and a second address within a second area of the nonvolatile memory. If the radio communication processor receives the first received data, then a controller stores the first write data in a volatile buffer. If there is no error in the first write data, then the controller reads out the first write data from the volatile buffer and stores the first write data in the first area. If the radio communication processor receives the second received data, then the controller stores the second write data in the second area without storing the second write data in the volatile buffer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 11, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takahiko Sato
  • Publication number: 20200251551
    Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.
    Type: Application
    Filed: January 3, 2020
    Publication date: August 6, 2020
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Youichi Okita, Wensheng Wang, Kazuaki Takai
  • Publication number: 20200127107
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor area of a first conductive type disposed in a surface layer portion of the semiconductor substrate, a gate electrode disposed over the first semiconductor area and extending in a first direction, a dummy gate electrode disposed over the semiconductor substrate away from the gate electrode and extending in the first direction, a second semiconductor area of a second conductive type disposed, in the surface layer portion of the semiconductor substrate, between the gate electrode and the dummy gate electrode, and an interconnect connected to the second semiconductor area, wherein a concentration of carrier of a first carrier type in the semiconductor substrate under the dummy gate electrode and alongside the second semiconductor area is lower than a concentration of majority carrier in the first semiconductor area, the first carrier type being a same carrier type as the majority carrier.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 23, 2020
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masaya Katayama
  • Patent number: 10573644
    Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: David A. Kidd
  • Publication number: 20200035273
    Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 30, 2020
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Keizo Morita
  • Patent number: 10546773
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Publication number: 20190385905
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Application
    Filed: August 27, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 10510824
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasuda
  • Publication number: 20190371419
    Abstract: A control circuit controls a column decoder and a row decoder to perform reprogramming where, before the count of reprogramming operations involving erasures, each targeting one of a plurality of memory cells included in a memory cell array, reaches a predetermined number, a first extent (e.g. a sub-block) including the targeted memory cell and being smaller than the entire extent of the memory cell array is used as the unit of reprogramming, and when the count of reprogramming operations reaches the predetermined number, a second extent (e.g. the memory cell array corresponding to one sector) including the targeted memory cell and being larger than the first extent is used as the unit of reprogramming, and resets the count of reprogramming operations each time it reaches the predetermined number.
    Type: Application
    Filed: May 2, 2019
    Publication date: December 5, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda
  • Publication number: 20190363195
    Abstract: A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.
    Type: Application
    Filed: February 12, 2019
    Publication date: November 28, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda
  • Publication number: 20190333580
    Abstract: A nonvolatile semiconductor memory device includes a selection transistor and a memory transistor that are formed on a well for each of a plurality of memory cells. At a time of a data read from the memory transistor, a first voltage is applied to the well and a source of the memory transistor, and a second voltage is applied to a gate of the selection transistor included in a non-selected memory cell among the plurality of memory cells. The first voltage is smaller than an absolute value of the second voltage.
    Type: Application
    Filed: January 31, 2019
    Publication date: October 31, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Shu Ishihara
  • Publication number: 20190326386
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasudo
  • Publication number: 20190326385
    Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Nobuhiro Misawa, Kazuyuki Kumeno, Makoto Yasudo
  • Patent number: 10432107
    Abstract: A rectifier circuit including a switch element, controls connection and disconnection of an AC input voltage using the switch element to generate an output voltage. The switch element includes an n-channel MOS transistor. The rectifier circuit further includes a booster circuit and a control signal generation unit, and establishes connection to the switch element at a peak portion of the input voltage. The booster circuit is configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor. The control signal generation unit is configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 1, 2019
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Satoshi Yamada
  • Publication number: 20190267320
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10373952
    Abstract: A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. The thickness of the gate insulating film in one of the first and second transistors is made larger than the thickness of the gate insulating film in the other one.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 6, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazushi Fujita
  • Publication number: 20190237471
    Abstract: A semiconductor device includes a substrate; a transistor formed on a surface of the substrate; a first insulating film formed above the transistor; a second semiconductor film formed on the first semiconductor film; a third semiconductor film formed on the second semiconductor film; a fourth semiconductor film formed on the third semiconductor film; and a ferroelectric capacitor formed on the fourth insulating film, wherein a hydrogen permeability of the third insulating film is higher than a hydrogen permeability of the first insulating film, and a hydrogen permeability and an oxygen permeability of the second insulating film and of the fourth insulating film are higher than the hydrogen permeability and an oxygen permeability of the first insulating film and of the third insulating film.
    Type: Application
    Filed: January 3, 2019
    Publication date: August 1, 2019
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kouichi Nagai, Ko Nakamura, Mitsuhiro Nakamura, Akio Ito