Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

Abstract: A radio communication processor receives first received data including first write data, a first address within a first area of a nonvolatile memory, and error detection information or second received data including second write data whose data amount is larger than a data amount of the first write data and a second address within a second area of the nonvolatile memory. If the radio communication processor receives the first received data, then a controller stores the first write data in a volatile buffer. If there is no error in the first write data, then the controller reads out the first write data from the volatile buffer and stores the first write data in the first area. If the radio communication processor receives the second received data, then the controller stores the second write data in the second area without storing the second write data in the volatile buffer.

Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.

Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: A rectifier circuit including a switch element, controls connection and disconnection of an AC input voltage using the switch element to generate an output voltage. The switch element includes an n-channel MOS transistor. The rectifier circuit further includes a booster circuit and a control signal generation unit, and establishes connection to the switch element at a peak portion of the input voltage. The booster circuit is configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor. The control signal generation unit is configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit.

Abstract: A semiconductor device includes a substrate; a transistor formed on a surface of the substrate; a first insulating film formed above the transistor; a second semiconductor film formed on the first semiconductor film; a third semiconductor film formed on the second semiconductor film; a fourth semiconductor film formed on the third semiconductor film; and a ferroelectric capacitor formed on the fourth insulating film, wherein a hydrogen permeability of the third insulating film is higher than a hydrogen permeability of the first insulating film, and a hydrogen permeability and an oxygen permeability of the second insulating film and of the fourth insulating film are higher than the hydrogen permeability and an oxygen permeability of the first insulating film and of the third insulating film.

Abstract: A radio communication processor receives data to which identification information is assigned and transmits a response signal indicative of whether or not application processing based on the data is normally performed. An application controller controls the application processing on the basis of the data and detects whether or not the application processing is normally performed. A controller detects on the basis of the identification information that the same data are received in succession due to retransmission, nullifies, when the application controller detects that the application processing based on the data received earlier is normally performed, control of the application processing based on the data received later to be performed by the application controller and instructs the radio communication processor to transmit the response signal which indicates that the application processing is normally performed.

Abstract: A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.

Abstract: A regulator circuit includes a first transistor reducing an external supply voltage and outputting an internal active voltage to an output node; a first detector receiving a criteria level, detecting the internal active voltage based on an enable signal, controlling a gate voltage of the first transistor, and adjusting an output current thereof; a second transistor reducing the external supply voltage, and outputting an internal standby voltage corresponding to the internal active voltage to the output node; a second detector receiving a reference voltage, detecting the internal standby voltage regardless of the enable signal, controlling a gate voltage of the second transistor, and adjusting an output current thereof; a first switch controlling whether to output the reference voltage as the criteria level of the first detector; and a second switch controlling whether to output the voltage of the output node as the criteria level of the first detector.

Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.

Abstract: A radio communication processor receives first received data including first write data, a first address within a first area of a nonvolatile memory, and error detection information or second received data including second write data whose data amount is larger than a data amount of the first write data and a second address within a second area of the nonvolatile memory. If the radio communication processor receives the first received data, then a controller stores the first write data in a volatile buffer. If there is no error in the first write data, then the controller reads out the first write data from the volatile buffer and stores the first write data in the first area. If the radio communication processor receives the second received data, then the controller stores the second write data in the second area without storing the second write data in the volatile buffer.

Abstract: A radio communication processor receives data to which identification information is assigned and transmits a response signal indicative of whether or not application processing based on the data is normally performed. An application controller controls the application processing on the basis of the data and detects whether or not the application processing is normally performed. A controller detects on the basis of the identification information that the same data are received in succession due to retransmission, nullifies, when the application controller detects that the application processing based on the data received earlier is normally performed, control of the application processing based on the data received later to be performed by the application controller and instructs the radio communication processor to transmit the response signal which indicates that the application processing is normally performed.

Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.

Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Abstract: A rectifier circuit including a switch element, controls connection and disconnection of an AC input voltage using the switch element to generate an output voltage. The switch element includes an n-channel MOS transistor. The rectifier circuit further includes a booster circuit and a control signal generation unit, and establishes connection to the switch element at a peak portion of the input voltage. The booster circuit is configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor. The control signal generation unit is configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit.

Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.