Patents Assigned to Fujitsu
  • Patent number: 7199745
    Abstract: A successive approximation A/D converter includes a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1, a switched capacitor D/A converter coupled to the sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, the switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce a comparison analog voltage responsive to the internal analog voltage and the control signal, a comparator coupled to the switched capacitor D/A converter to produce a comparison result signal responsive to the comparison analog voltage, and a control circuit coupled to the comparator to supply the control signal responsive to the comparison result signal to the switched capacitor D/A converter.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Suguru Tachibana, Kazuhiro Mitsuda, Tatsuo Kato
  • Patent number: 7197813
    Abstract: The magnetoresistance is measured for a magnetoresistive layered-structure, such as a spin valve film, prior to formation of an upper shield layer as well as patterning of a lower shield layer. The magnetic influence of the upper and lower shield layers can completely be eliminated during the measurement of the magnetoresistance. The magnetoresistive layered-structure is allowed to reliably receive the magnetic field over a wider range including a lower magnetic field range. It is accordingly possible to measure the magnetoresistance properly reflecting the magnetic characteristic of the magnetoresistive layered-structure. It is possible to find deficiency of a magnetoresistive read element at an earlier stage of the method.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Naoki Mukoyama, Kenichiro Yamada, Hitoshi Kanai, Manabu Watanabe, Norikazu Ozaki, Kazuaki Satoh
  • Patent number: 7200510
    Abstract: A measurement control apparatus designed to automatically select an interface circuit compatible with a measurement controlled object without error. A measurement control processor outputs interface setting data for setting one interface circuit compatible with the measurement controlled object in advance of output of measurement control data to the measurement controlled object. Based on this, an interface setting means activates only that interface circuit. Further, the processor is provided with a loopback unit for returning the interface setting data to the measurement control processor and confirms the match of the output interface setting data and the returned interface setting data. Further, it is provided with an identification code setting means for setting an identification code unique to an interface board mounting the interface circuit and confirms that the interface board has been correctly selected.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Ten Limited
    Inventors: Takeshi Yasuda, Takashi Shimizu
  • Patent number: 7199985
    Abstract: A magnetic sensor including a ferromagnetic tunnel junction, comprises a free layer 10 a magnetic direction of which freely rotates, and a barrier layer 11 formed on the free layer and reduces a thickness in a first region, the free layer in a region corresponding to the first region functioning as a sensor portion for sensing an external magnetic field. Such magnetic sensor can provide magnetic sensors, magnetic heads and magnetic encoders having high sensitivity. Furthermore, such magnetic sensor can provide magnetic heads which are adaptable to high recording density of magnetic storage mediums, and hard disk devices of large storage capacities using the magnetic heads.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Masashige Sato, Hideyuki Kikuchi, Kazuo Kobayashi
  • Patent number: 7200029
    Abstract: A ferroelectric storage device includes a ferroelectric capacitor C1, a bit line BL, a first switching element 103 selectively connecting the ferroelectric capacitor C1 and the bit line BL, a first transistor 203 connected to the bit line BL and to a reference potential, a reference ferroelectric capacitor CR1, a reference bit line Lref, a reference switching element 105 selectively connecting the reference ferroelectric capacitor CR1 and the reference bit line Lref, a second transistor 201 connected to the reference bit line Lref and to the reference potential, potential control circuits 110 and 200 controlling a potential of the bit line BL and a potential of the reference bit line Lref, and a timing control circuit 210 controlling a detection timing for detecting data on the bit line.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Yoshioka
  • Publication number: 20070069384
    Abstract: A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A , a second metal layer 113 formed in the hole 112A , a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.
    Type: Application
    Filed: January 26, 2006
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Kenichi Watanabe
  • Publication number: 20070072444
    Abstract: A connector module that is mounted on a motherboard and is configured to realize connection between a cable side connector and the motherboard is disclosed. The connector module includes a printed circuit board, plural substrate side connectors that are mounted on the front surface of the printed circuit board and arranged into plural rows with differing heights, and a mounting connector that is mounted on the rear surface of the printed circuit board. At least one of the substrate side connectors is connected to the cable side connector. The mounting connector is engaged with and connected to a motherboard side connector that is mounted on the motherboard. The printed circuit board includes a pattern that is configured to realize electrical connection between the substrate side connectors and the mounting connector.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: FUJITSU COMPONENT LIMITED
    Inventors: Takeshi Okuyama, Haruna Morohoshi, Mitsuru Kobayashi, Tadashi Kumamoto, Takahiro Kondou
  • Publication number: 20070072457
    Abstract: A connector comprises: a shield cover; a connector module housed in the shield cover; an insertion portion disposed at a tip thereof, the insertion portion being configured to be inserted into a destination connector and having signal contacts and ground contacts arranged; and a cable extending from a rear end of the connector. The connector module includes a printed board, the signal contacts, and the ground contacts. The printed board includes signal and ground patterns on front and rear faces, the signal pattern having pads for signal contacts and the ground pattern having pads for ground contacts. The signal contacts are formed based on the pads for signal contacts and fixed on the pads for signal contacts. The ground contacts are formed based on the pads for ground contacts and fixed on the pads for ground contacts. The insertion portion is formed at an end of the printed board.
    Type: Application
    Filed: April 20, 2006
    Publication date: March 29, 2007
    Applicant: Fujitsu Component Limited
    Inventor: Masahiro Hamazaki
  • Publication number: 20070072164
    Abstract: A pointing information extraction unit extracts pointing information indicating a pointing position and a pointing time on a slide from a slide file used in a lecture and a video file of a lecture video using a pointing device. A word information generation unit analyzes a text sentence extracted from the slide file to generate a word information file indicating a word and a position thereof. A word pointing information generation unit estimates a word closest to the pointing position on the slide to generate a word pointing information file with the pointing time assigned. A fill-in-the-blank word extraction unit extracts a word having a pointing time equal to or longer than a predetermined time from the word pointing information as a fill-in-the-blank word file. A fill-in-the-blank test question is generated by setting the fill-in-the-blank word of the slide information as a blank region.
    Type: Application
    Filed: December 22, 2005
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yutaka Katsuyama, Noriaki Ozawa, Satoshi Naoi
  • Publication number: 20070070492
    Abstract: An optical amplifier is provided with a controlling unit for controlling a gain of the optical amplifier based on input light power and output light power of the optical amplifier, as well as a gain control amount variable unit for changing the gain control amount of the optical amplifier by the controlling unit according to at least one of the input light power and the output light power. Thereby, optical communication, which can follow the change in the input power of the optical amplifier in high speed and also is stable, can be realized, without causing the occurrence of an oscillation phenomenon, the large size of the optical amplifier, and the increase in power consumption and heating.
    Type: Application
    Filed: November 29, 2006
    Publication date: March 29, 2007
    Applicant: Fujitsu Limited
    Inventors: Masato Oota, Nobukazu Koizumi, Yohei Koganei
  • Publication number: 20070070064
    Abstract: When three-dimensional shape information is represented by a feature-based model, a fillet/chamfer feature is searched for and accumulated. When three-dimensional shape information is not represented by a feature-based model, information of a fillet surface/chamfer surface is searched for and accumulated. From corner shapes accumulated, a corner shape to be removed is selected. The feature or the information of the surface element selected is removed from the three-dimensional shape information. Projection is performed on the basis of the three-dimensional information after the removal, thereby obtaining two-dimensional shape information.
    Type: Application
    Filed: March 7, 2006
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Masahito Nasu
  • Publication number: 20070070977
    Abstract: A mobile terminal system transmits a request message to a delivering source system. The request message specifies resources to be delivered, and a relay system for receiving the resources. The delivering source system delivers the specified resources to the specified relay system according to the request message. The relay system holds the resources. The mobile terminal system is connected to the relay system, and receives the resources from the relay system.
    Type: Application
    Filed: November 2, 2006
    Publication date: March 29, 2007
    Applicant: Fujitsu Limited
    Inventors: Masaya Kimura, Katzumi Hayashi, Taichi Ujigawa, Yasutaka Oda
  • Publication number: 20070069036
    Abstract: The present invention provides a RFID tag that includes a base, an antenna for communication wired to the base, a circuit chip electrically connected to the antenna for radio communication via the antenna, a first reinforcing member and a second reinforcing member. The first reinforcing member covers and fills the whole of the circuit chip and part of the antenna. The second reinforcing member is positioned underside of the first reinforcing member across the base and has an edge that is displaced from the edge of the first reinforcing member at least in the point where the edge of the first reinforcing member meets the antenna.
    Type: Application
    Filed: December 7, 2005
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Shunji Baba
  • Publication number: 20070072382
    Abstract: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S7), introducing a diffusion-suppressing substance into the semiconductor substrate to suppress the diffusion of the impurity (step S8), forming a side wall-insulating film on each side surface of the gate electrode (step S9), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S10), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S11), and further activating the impurity by the millisecond annealing treatment (step S12).
    Type: Application
    Filed: December 14, 2005
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Tomonari Yamamoto, Tomohiro Kubo
  • Publication number: 20070071281
    Abstract: An embedding-availability determining unit determines an availability of embedding data into an image based on an input/output characteristic of a predetermined feature amount related to a combination of an output device that outputs an image in which the data is embedded to a medium and an input device that inputs the image that is output to the medium. A result output unit outputs a result of determination by the embedding-availability determining unit.
    Type: Application
    Filed: December 30, 2005
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Hirotaka Chiba, Tsugio Noda
  • Publication number: 20070073924
    Abstract: A DMA transfer system includes a DMA controller having at least one channel coupled to a system bus, the DMA controller configured to perform a DMA transfer via the system bus according to a DMA transfer setting of the at least one channel, and a DMAC control unit coupled to the DMA controller, wherein the DMAC control unit includes a plurality of virtual channels configured to have respective DMA transfer settings made thereto, a virtual channel arbiter configured to select one of the plurality of virtual channels, and a DMA setting circuit configured to read a DMA transfer setting of the selected virtual channel to write the read DMA transfer setting to the at least one channel of the DMA controller.
    Type: Application
    Filed: February 24, 2006
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Kenichiro Kuroki, Kenji Sato
  • Publication number: 20070070314
    Abstract: In performing exposure for forming patterns being fine as well as having great density difference, adequate corrections are to be enabled for suppressing the influence from peripheries of these patterns to be a minimum and for suppressing the dimension variation within the plane of semiconductor substrate or among semiconductor substrates to a minimum. So-called lower-layer corrections are executed, in order to suppress the three-dimensional influence, namely the influence of the film-thickness distribution of a lower-layer structure body lying under a subject film to be processed with a resist. A pattern-correcting portion adjusts the amount of exposure such that it cancels the in-plane film-thickness distribution of the lower-layer structure body in respective exposure regions.
    Type: Application
    Filed: December 21, 2005
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Keiji Yamada
  • Publication number: 20070070535
    Abstract: A storage system is constructed by a hierarchy of a primary storage device and a secondary storage device. A storage system has a hierarchy of a primary storage device, secondary storage devices and a storage processor, an emulator device for emulating an identifier of a maintenance target unit. The emulator device is installed between the installation port of the maintenance target unit and the maintenance target unit, so that the storage system cannot recognize changes even if the maintenance target unit is replaced. By this, a complicated setup operation required to replace the maintenance target unit becomes unnecessary, and operation errors can be prevented.
    Type: Application
    Filed: March 2, 2006
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Hirokazu Fujitani
  • Publication number: 20070070400
    Abstract: In an information processing apparatus capable of communicating with an information managing apparatus capable of managing information stored in the information processing apparatus, the information processing apparatus is comprised of: storage means for storing thereinto identification information which identifies predetermined information from the stored information so as to call the identified information from the information managing apparatus; identification information managing means for editing the identification information stored in the storage means so as to manage the edited identification information; and information transmitting/receiving means for instructing an acquisition of the stored information in order that information managed in the identification information managing means is transmitted to the information managing apparatus, and for transmitting/receiving the identification information and the stored information with respect to the information managing apparatus.
    Type: Application
    Filed: March 24, 2006
    Publication date: March 29, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Yasuhiro Matsumura
  • Publication number: 20070071447
    Abstract: An optical receiving apparatus has a route change detector for detecting occurrence of a route change of received signal light, a memory for beforehand storing optimum dispersion compensation quantity for the received signal light before and after the route change, a tunable dispersion compensator for compensating dispersion of the received signal light, and a controller for controlling a dispersion compensation quantity used by the tunable dispersion compensator according to the optimum dispersion compensation quantity for the received signal light after the route change, which is beforehand stored in the memory, when the route change detector detects occurrence of the route change. The dispersion compensation quantity can be optimized at high-speed for each of optical transmission routes of the received signal light.
    Type: Application
    Filed: December 22, 2005
    Publication date: March 29, 2007
    Applicant: Fujitsu Limited
    Inventors: Masakazu Ozaki, Katsumi Fukumitsu