Patents Assigned to Fulcrum Microsystems, Inc.
  • Patent number: 8495543
    Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: July 23, 2013
    Assignees: University of Southern California, Fulcrum Microsystems, Inc.
    Inventors: Georgios Dimou, Peter A. Beerel, Andrew Lines
  • Patent number: 8448105
    Abstract: Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: May 21, 2013
    Assignees: University of Southern California, Fulcrum Microsystems, Inc.
    Inventors: Georgios Dimou, Peter A. Beerel, Andrew Lines
  • Patent number: 8098574
    Abstract: Global ports are supported in multi-switch systems having arbitrary topologies. In some implementations, global ports are implemented in a manner which makes the switch system robust in the face of link failure. In specific Ethernet implementations, global ports enable flooding, learning, forwarding, and link aggregation across the switch system.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: January 17, 2012
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Robert Southworth, Uri Cummings, Zhi-Hern Loh
  • Patent number: 8086975
    Abstract: Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: December 27, 2011
    Assignees: University of Southern California, Fulcrum Microsystems, Inc.
    Inventors: Ken Shiring, Peter A. Beerel, Andrew Lines, Arash Saifhashemi
  • Patent number: 8051396
    Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 1, 2011
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Peter Beerel, Andrew Lines, Michael Davies
  • Patent number: 7916718
    Abstract: A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: March 29, 2011
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Zhi-Hern Loh, Michael Davies, Uri Cummings
  • Patent number: 7821925
    Abstract: Methods and apparatus are described for assigning data units to a plurality of groups. A key is generated for each of the data units such that the keys corresponding to associated ones of the data units are identical. An initial hash value is generated for each of the keys. A number of techniques are described for then deterministically scrambling the initial hash values such that small bit changes in the keys will typically produce stochastically large changes in the final hash values. The data units are mapped to specific ones of the groups with reference to the scrambled hash values.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: October 26, 2010
    Assignee: Fulcrum Microsystems, Inc.
    Inventor: Michael Davies
  • Patent number: 7814280
    Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 12, 2010
    Assignee: Fulcrum Microsystems Inc.
    Inventors: Uri Cummings, Andrew Lines, Patrick Pelletier, Robert Southworth
  • Patent number: 7698535
    Abstract: An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: April 13, 2010
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Andrew Lines, Robert Southworth, Uri Cummings
  • Patent number: 7584449
    Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: September 1, 2009
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Peter Beerel, Andrew Lines, Michael Davies
  • Patent number: 7283557
    Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: October 16, 2007
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines
  • Patent number: 7274710
    Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 25, 2007
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines
  • Patent number: 7274709
    Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 25, 2007
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines
  • Patent number: 7260753
    Abstract: Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: August 21, 2007
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Michel A. Moacanin, Jeremy Boulton, Steven Novak
  • Patent number: 7239669
    Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: July 3, 2007
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines
  • Patent number: 7161828
    Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: January 9, 2007
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines
  • Publication number: 20060239392
    Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
    Type: Application
    Filed: June 21, 2006
    Publication date: October 26, 2006
    Applicant: Fulcrum Microsystems, Inc., A California corporation
    Inventors: Uri Cummings, Andrew Lines
  • Publication number: 20060155938
    Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.
    Type: Application
    Filed: August 18, 2005
    Publication date: July 13, 2006
    Applicant: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines, Patrick Pelletier, Robert Southworth
  • Patent number: 7050324
    Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: May 23, 2006
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Uri Cummings, Andrew Lines
  • Publication number: 20050276095
    Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.
    Type: Application
    Filed: August 9, 2005
    Publication date: December 15, 2005
    Applicant: Fulcrum Microsystems Inc.
    Inventors: Uri Cummings, Andrew Lines