Patents Assigned to Fulcrum Microsystems, Inc.
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Publication number: 20080181103Abstract: Methods and apparatus are described for assigning data units to a plurality of groups. A key is generated for each of the data units such that the keys corresponding to associated ones of the data units are identical. An initial hash value is generated for each of the keys. A number of techniques are described for then deterministically scrambling the initial hash values such that small bit changes in the keys will typically produce stochastically large changes in the final hash values. The data units are mapped to specific ones of the groups with reference to the scrambled hash values.Type: ApplicationFiled: January 29, 2007Publication date: July 31, 2008Applicant: FULCRUM MICROSYSTEMS INC.Inventor: Michael Davies
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Patent number: 7283557Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.Type: GrantFiled: April 30, 2002Date of Patent: October 16, 2007Assignee: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines
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Patent number: 7274710Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.Type: GrantFiled: September 6, 2002Date of Patent: September 25, 2007Assignee: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines
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Patent number: 7274709Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.Type: GrantFiled: September 6, 2002Date of Patent: September 25, 2007Assignee: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines
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Patent number: 7260753Abstract: Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment.Type: GrantFiled: July 25, 2003Date of Patent: August 21, 2007Assignee: Fulcrum Microsystems, Inc.Inventors: Michel A. Moacanin, Jeremy Boulton, Steven Novak
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Patent number: 7239669Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.Type: GrantFiled: August 4, 2003Date of Patent: July 3, 2007Assignee: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines
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Patent number: 7161828Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.Type: GrantFiled: August 9, 2005Date of Patent: January 9, 2007Assignee: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines
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Publication number: 20060239392Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.Type: ApplicationFiled: June 21, 2006Publication date: October 26, 2006Applicant: Fulcrum Microsystems, Inc., A California corporationInventors: Uri Cummings, Andrew Lines
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Publication number: 20060155938Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.Type: ApplicationFiled: August 18, 2005Publication date: July 13, 2006Applicant: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines, Patrick Pelletier, Robert Southworth
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Patent number: 7050324Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.Type: GrantFiled: July 13, 2004Date of Patent: May 23, 2006Assignee: Fulcrum Microsystems, Inc.Inventors: Uri Cummings, Andrew Lines
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Publication number: 20050276095Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.Type: ApplicationFiled: August 9, 2005Publication date: December 15, 2005Applicant: Fulcrum Microsystems Inc.Inventors: Uri Cummings, Andrew Lines
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Patent number: 6961863Abstract: An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.Type: GrantFiled: October 25, 2002Date of Patent: November 1, 2005Assignee: Fulcrum Microsystems Inc.Inventors: Michael I. Davies, Andrew Lines, Robert Southworth
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Patent number: 6854096Abstract: Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.Type: GrantFiled: July 14, 2003Date of Patent: February 8, 2005Assignee: Fulcrum Microsystems, Inc.Inventors: Frederik Eaton, Peter Beerel
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Publication number: 20050024928Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.Type: ApplicationFiled: July 13, 2004Publication date: February 3, 2005Applicant: Fulcrum Microsystems Inc.Inventors: Uri Cummings, Andrew Lines
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Publication number: 20050013356Abstract: Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment.Type: ApplicationFiled: July 25, 2003Publication date: January 20, 2005Applicant: Fulcrum Microsystems Inc.Inventors: Michel Moacanin, Jeremy Boulton, Steven Novak
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Patent number: 6785875Abstract: Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.Type: GrantFiled: January 28, 2003Date of Patent: August 31, 2004Assignee: Fulcrum Microsystems, Inc.Inventors: Peter Beerel, Andrew Lines, Qing Wu
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Publication number: 20040151209Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.Type: ApplicationFiled: August 4, 2003Publication date: August 5, 2004Applicant: Fulcrum Microsystems Inc. A California CorporationInventors: Uri Cummings, Andrew Lines
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Publication number: 20040111589Abstract: An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.Type: ApplicationFiled: September 16, 2003Publication date: June 10, 2004Applicant: Fulcrum Microsystems, Inc., a California corporationInventors: Andrew Lines, Robert Southworth, Uri Cummings
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Publication number: 20040103377Abstract: Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.Type: ApplicationFiled: July 14, 2003Publication date: May 27, 2004Applicant: Fulcrum Microsystems, Inc.Inventors: Frederik Eaton, Peter Beerel
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Publication number: 20040100900Abstract: A message unit for transmitting messages in a data processing system characterized by an execution cycle is described. The message unit includes a message array and message transfer circuitry. The message transfer circuitry is operable to facilitate transfer of a message stored in a first portion of the message array in response to a first message transfer request. The message transfer circuitry is further operable to store up to one additional message transfer request per execution cycle while facilitating transfer of the message, and to maintain strict ordering between overlapping requests.Type: ApplicationFiled: May 30, 2003Publication date: May 27, 2004Applicant: Fulcrum Microsystems, Inc.Inventors: Andrew Lines, Craig Stoops, Eric Peterson, Alain Gravel