Abstract: An inverter comprises a first switch coupled to an input of an output filter and a positive dc bus, a second switch coupled to the input of the output filter and a negative dc bus, a first freewheeling apparatus coupled to the first switch, the second switch and ground, a first soft switching network coupled to the first freewheeling apparatus and the first switch, wherein the first soft switching network is configured such that the first switch is of a first zero voltage transition during a turn-on process of the first switch and a second soft switching network coupled to the first freewheeling apparatus and the second switch, wherein the second soft switching network is configured such that the second switch is of a second zero voltage transition during a turn-on process of the second switch.

Abstract: An apparatus comprising a processor configured to determine whether to apply an intra smoothing filter for a prediction unit (PU) based on a lookup table (LUT), wherein the LUT comprises data indicating the intra smoothing filter should not be applied for any PU with a block size of 8×8 pixels and associated with directional prediction mode. The disclosure also includes a method comprising generating reference samples, determining a size of a PU block, and selecting the reference samples based on PU block size, wherein filtered reference samples are not selected for PU blocks with a size of 8×8 pixels and associated with directional prediction mode.

Abstract: An inverter comprises a first boost apparatus having an input coupled to a positive dc bus, a second boost apparatus having an input coupled to a negative dc bus, a first switch coupled to an input of an L-C filter and the first boost apparatus, a second switch coupled to the input of the L-C filter and the second boost apparatus, a third switch coupled between the positive dc bus and the first switch, wherein a common node of the first switch and the third switch is directly connected to an output of the first boost apparatus, a fourth switch coupled between the negative dc bus and the second switch, wherein a common node of the fourth switch and the second switch is directly connected to an output of the second boost apparatus and an isolation switch coupled between the input of the L-C filter and ground.

Abstract: A method for operating a communications controller includes defining a positive integer quantity of resource element groups from a resource block with a positive integer number N resource elements in each resource element group, the resource block having a total number of resource elements, the total number of resource elements consisting of available resource elements and reserved resource elements. The method also includes assigning a plurality of available resource elements to fill in each of the positive integer quantity of resource element groups with N available resource elements in each resource element group, and blocking any unassigned available resource elements from being used in a resource element group. The method further includes interleaving a plurality of control messages onto the positive integer quantity of resource element groups, and transmitting the positive integer quantity of resource element groups.

Abstract: A processor executes instructions stored in non-transitory memory storage to receive a pattern query for a graph and determine a set of access constraints corresponding to the pattern query. A determination is made whether the pattern query is effectively bounded under the set of access constraints. A query plan is formed to retrieve a subgraph of the graph when the pattern query is effectively bounded under the set of access constraints. The answer to the pattern query is obtained by accessing the at least one subgraph in response to the query plan.

Abstract: A network element (NE) comprising a receiver configured to couple to a cloud network; and a multi-core central processing unit (CPU) coupled to the receiver and configured to receive a first partition configuration from an orchestration element, partition a plurality of processor cores into a plurality of processor core partitions according to the first partition configuration, and initiate a plurality of virtual basic input/output systems (vBIOSs) such that each vBIOS manages a processor core partition.

Abstract: An apparatus in a user equipment node (UE) is configured to perform a method for channel feedback. The method includes determining, based on a common reference signal received from a base station and one or more channel conditions, a plurality of values for a receiver table. The method also includes determining a plurality of values for a decision table based on corresponding values in the receiver table and a predetermined interference table. The method further includes selecting a value from the decision table. In addition, the method includes transmitting, to the base station, at least one of a rank indicator (RI) value and a precoding matrix indicator (PMI) value associated with the selected value in the decision table.

Abstract: A method for channel estimation includes determining position information of a main transmission point with a primary transmission path to the communications device and of at least one mirror transmission point associated with the main transmission point by at least one secondary transmission path between the main transmission point and the communications device, estimating a primary channel between the main transmission point and the communications device and at least one secondary channel between the at least one mirror transmission point and the communications device in accordance with the position information of the main transmission point and of the at least one mirror transmission point and position information of antennas in an antenna array of the communications device, and instructing use of the estimated primary channel and the at least one estimated secondary channel.

Abstract: A multiple disk loader apparatus includes a plurality of rods. Each rod has a pair of pins extending radially from a side of the rod. The pair of pins are spaced circumferentially around the rod with respect to each other. Each pin has a top surface wherein the top surface of a first pin is longitudinally separated from the top surface of a second pin by a predetermined gap. A rotation device is coupled to the plurality of rods. The rotation device rotates the plurality of rods individually through a respective predetermined arc and in a respective rotational direction in order to extract a disk stack from storage and to separate a disk from the stack to load into a drive.

Abstract: An apparatus for interconnecting a fiber-optic network and a coax network comprising a coax line terminal (CLT) configured to couple to an optical line terminal (OLT) at the fiber-optic network and a plurality of coax network units (CNUs) at the coax network and to cache data received from the CNUs and forward the cached data to the OLT upon receiving a message from the OLT that assigns a transmission cycle for a specified CNU, wherein the CLT forwards the cached data to the OLT upon receiving the message regardless of whether the cached data corresponds to the specified CNU.

Abstract: Signaling and verifying URL signatures for accessing URL addressable content in adaptive streaming. A plurality of URL authentication and URL authorization descriptors are provided for a plurality of URLs, wherein each URL authentication descriptor comprises information for verification key acquisition and for accessing an authentication tag for authenticating a given URL in the plurality of URLs according to an associated URL authentication scheme. Each URL authorization descriptor is for verification key acquisition and for accessing an authorization tag for authorizing access to content addressable by a given URL in the plurality of URLs according to an associated URL authentication scheme. A plurality of URL authentication and URL authorization descriptors for the plurality of URLs are communicated and each descriptor is verified in the communicated plurality of URL authentication and URL authorization descriptors for its given URL in the plurality of URLs according to its associated scheme.

Abstract: An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

Abstract: A method implemented by a network device in a wireless system is provided. The method includes obtaining a plurality of electronic signals and selecting a first group of signals and a second group of signals from the plurality of electronic signals, generating phase conjugated copies of signals in the first group of signals, and aggregating the phase conjugated copies and a second group of signals into sub-bands in a frequency domain via frequency-domain multiplexing (FDM), wherein the phase conjugated copies are spectrally inverted in the frequency domain. The method may include converting the aggregated electronic signal to an aggregated optical signal, and transmitting the aggregated optical signal over a fiber link.

Abstract: When at least one of device-to-device UEs in connections of a group of D2D UEs is outside of the coverage area of mobile network of an access point, an information exchange mechanism established directly between the D2D UEs, without involving a third party, is provided. A resource allocation method for a device-to-device (D2D) communication link between two or more D2D user equipments (UEs) in a mobile communication network is provided according to an example.

Abstract: A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

Abstract: A method comprises providing a buck-boost converter comprising a first high-side switch and a first low-side switch connected in series across an input capacitor, a second high-side switch and a second low-side switch connected in series across an output capacitor and an inductor coupled between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch, detecting a first voltage resonance waveform across a switch of the buck-boost converter and turning on the switch of the buck-boost converter when the first voltage resonance waveform falls to zero.

Abstract: A link cost determining method including computing, by a station, a new composite data rate using a set of data rates including an average data rate, a geometric mean data rate, and a minimum data rate for data samples, computing, by the station, a pair of hysteresis thresholds for a previous composite data rate, determining, by the station, whether the new composite data rate exceeds one of the pair of hysteresis thresholds, and advertising, by the station, the new composite data rate when the new composite data rate exceeds one of the pair of hysteresis thresholds.

Abstract: A configurable impedance circuit is provided, including a filter for filtering a received DC voltage and a controller. The filter includes a first capacitor, a second capacitor, and a selectable switch coupled in series with the second capacitor and coupled to receive a control signal. The selectable switch and the second capacitor are selectively coupled in parallel with the first capacitor. The controller is connected to sense a differential voltage across the second capacitor and configured to generate the control signal to open or close the selectable switch based on the differential voltage across the second capacitor, so as to maintain a voltage range across the second capacitor. According to disclosure of the present invention, the total physical size of the capacitors is reduced and the size of the power supply is reduced accordingly.

Abstract: A system and method of partitioning host processing system resources is provided. An integrated circuit device having a plurality of processors or processing cores and a number of interfaces is portioned at boot into different hardware partitions based on the application needs of the host processing system. The technology provides a non-transitory memory storage including instructions; and a plurality of processors in communication with the memory. The integrated circuit device also includes a plurality of communication interfaces in communication with the processors. At least one of the plurality of processors executes instructions to configure a subset of the plurality of processors to a first hardware partition, and configure a different subset of the plurality of processors and at least one of the plurality of communication interfaces to a second hardware partition.

Abstract: A configurable impedance circuit includes a controller that senses a rectified voltage and generates a first and second control signals based on a comparison of the rectified voltage to at least one threshold voltage. The configurable impedance circuit also includes a filter for filtering the rectified voltage that couples a plurality of capacitors in series to the rectified voltage in a first configuration based on the first control signal and couples the plurality of capacitors in parallel to the rectified voltage in a second configuration based on the second control signal.