Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

Abstract: In accordance with the invention, a circuit and a method for extracting a clock signal from a serial data stream are provided. A window pulse is generated such that transitions of a delayed version of the serial data stream occur near the center of the window pulse. A PUP signal and a PDN signal are generated having pulse widths indicative of the time at which transitions of the clock signal occur with respect to the window pulse. The PUP and PDN signals are used to generate a reference voltage to control the clock frequency. Window pulses may be generated in response to only positive transitions or to only negative transitions of the delayed serial data stream, or alternatively may be generated in response to both negative and positive transistions. The amount of delay introduced to the serial data stream may be selectively adjusted for different bit rates.

Abstract: In one embodiment, the threshold voltage of the electrostatic protection circuit is selectively raised above the power supply voltage by the inclusion of a plurality of serially connected diodes connected between the power supply voltage and a discharge reference rail. The serially connected diodes become forward biased when a voltage applied to the rail is above the power supply voltage by a voltage equal to the sum of the various voltage drops across the serially connected diodes.The various input pads of the integrated circuit are connected to an anode of an associated diode, wherein the cathode of the associated diode is connected to the discharge reference rail, rather than directly to V.sub.DD as in the prior art. The anodes of each of these diodes are also connected to the device to be protected within the integrated circuit.

Abstract: A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.

Abstract: In a current pump, three separate current sources, each providing an identical current, are used. A first current pump is provided between an output load and a positive power supply terminal to provide a positive current to a load. To enable the current pump to provide a zero current to the load or withdraw a current from the load, second and third current pumps are provided in parallel between the load and a ground terminal. Associated switches couple these second and third current sources to the load. Thus, three states of the current pump are available which provide either a positive current, a negative current, or a zero current to a load.

Abstract: A charge pump essentially incorporating parallel connections of low capacity charge pumps, where each low capacity charge pump is controlled by a clock signal, where the clock signal associated with a low capacity charge pump has a phase different than the other clock signals. Hence, the output of these essentially parallel connected charge pumps will have a ripple period which is a fraction of the period of any single clock signal, wherein the fraction is equal to 1/n, where n is the number of parallel low capacity charge pumps. This results in a ripple magnitude of 1/n that of charge pumps using a single clock source with identical input and output capacitance.

Abstract: The present electrical circuit functions to couple together circuits which may have different signal operating levels, such as circuits having small-swing ECL operating levels and large-swing TTL operating levels. The present circuit outputs a signal which is virtually unaffected by any non-ideal characteristics of transistors comprising the circuit.

Abstract: A switch means is disclosed which enables two or more terminals normally having a wide operating voltage to be connected by a pass transistor. A biasing means applies a voltage to the gate of the pass transistor which turns on the pass transistor without forward biasing any inherent diodes within the pass transistor.

Abstract: The present invention includes circuitry implemented in gallium arsenide technology for generating various substantially constant reference voltage and a substantially constant reference current for applications thereof as needed.

Abstract: In one embodiment, a semiconductor device which generates a substantially constant reference voltage over a broad temperature range upon application of a power supply voltage thereto, wherein a current substantially inversely proportional to the value of a load resistor is drawn through the resistor to generate a substantially constant voltage across the resistor. The current through the resistor is the sum of a first current and a second current. The first current is determined by the absolute value of the threshold voltage of a depletion mode FET (DFET) in conjunction with an associated first resistor. The second current is determined by the threshold voltage of an enhancement mode FET (EFET) in conjunction with an associated second resistor. As the temperature of the device changes the first and second currents will change in opposite directions with the sum being changed inversely proportional to the change in resistance with temperature of the load resistor.

Abstract: A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output terminal to immediately assume the state of the reset signal without any intervening gate delay.

Abstract: An output buffer provides high current at an output for only a brief period, while after this brief period the output buffer only supplies a limited amount of current to the subsequent stage. One embodiment of this inventive output buffer utilizes the inherent delay of an inverter and a high current FET device, arranged to form a feedback circuit, to switch off high current supplied to the subsequent stage afer a brief period. This brief period allows the output of the output buffer to supply the necessary current and voltage to switch the subsequent stage. A low current FET device in the output buffer then provides the necessary low current to maintain the state of the subsequent stage without supplying current unnecessary for the proper operation of the subsequent stage.

Abstract: This invention discloses an integrated circuit implemented in compound semiconductor technology including an input signal lead and an output signal lead, and buffer circuitry interconnecting those leads, the circuit being compatible with standard logic signals thereinto and therefrom.

Abstract: This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.

Abstract: This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Abstract: A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.

Abstract: A multiplexing type circuit includes circuit portions having input and output leads associated therewith, to allow testing of the individual circuit portions, and further includes laser programmable fuses which allow selective disconnection of certain input and output leads as chosen to disconnect circuit portions from the overall circuit as appropriate.

Abstract: This invention discloses a laser programmable read only semiconductor-based memory array comprised of memory cells, a group of word lines, a group of bit lines. Each of the memory cells is connected to one of the group of bit lines, and one of the group of word lines and each memory cell is comprised of a memory element and a laser programmable link. In one embodiment, each memory cell is comprised of a transistor and a laser programmable link composed of the same material as either the word or the bit lines. Programming is accomplished by laser coding of the links.

Abstract: An improved logic circuit is disclosed, of the type in which one or more input signals, generated by one or more input signal generator circuits, are referenced to a threshold voltage, determined by a threshold voltage generator circuit, to determine whether said one or more input signals are in a high or low state. In this improved logic circuit, the time constants of the input signal generator circuits are matched with those of the threshold voltage generator circuit so that any power supply perturbations commonly applied to the input signal generator circuits and threshold voltage generator circuit, such as due to the switching on or off of output loads, will result in these circuits having substantially identical frequency responses and amplitude versus time responses.

Abstract: A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously. In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device. To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path. The delay circuit detects the various differences in round-trip arrival times of the clock signal associated with each receiving device and fixes a particular clock signal delay for each receiving device so that subsequent clock signals will arrive at each receiving device simultaneoulsy.