Abstract: An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. The channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based on the lowest price (highest cost) ready channel, with the price of a channel being equal to the value of the channel select position counter divided by the number of selects for that channel in the frame, and the readiness of the channel being indicated either by an indicator, or by the relative value of the position counter to the initial value of the position counter. Where channel prices are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel contributing first. After a select is made, the position counter of the selected channel is increased by the total number of selects in the frame.

Abstract: Methods are provided for multiplexing a plurality of channels on to a sub-aggregate of an aggregate line so as to substantially minimize total frame length. In a preferred method, channel data rates are expressed as a sum of a plurality of predetermined subchannel data rates, and the number of times each predetermined subchannel data rate is used to express a channel data rate of a channel to be multiplexed is accumulated. Given a predetermined primary frame rate (P) such as 8Khz for a DACs compatible multiplexer, and a tertiary frame rate (T) chosen as the greatest common denominator of the subchannel data rates, an optimal secondary frame rate (S) may be found by minimizing for a plurality of different secondary frame rates the sum of (P/S) F1 plus (S/T)F2, where F1 represents the number of calls of the primary frame to the secondary frame, and F2 represents the number of calls of the secondary frame to the tertiary frame.

Abstract: This invention relates to an improved captive screw and assembly, and particularly a screw which may be held loosely captive in the threaded hole of a support member. The invention comprises a machine screw or cold formed fastener with an unthreaded interrupted mid-section that separates two spaced-apart threaded portions of the fastener, with both threaded portions of the fastener preferably of a similar thread size, and with the unthreaded mid-section of the screw of a diameter less than the root diameter of the threaded sections. The screw may be completely removed or readily installed into threaded engagement with a female threaded hole in the support member, when necessary, by first manually aligning the fastener axis with the axis of the threaded hole, then rotating the fastener to engage the starting threads of the fastener with those of the female threaded hole, and further continued rotating of the fastener in a conventional manner. The fastener may clamp a panel member to the support member.

Abstract: A serial arithmetic processor arranged to perform the complex arithmetic functions of the Adaptive Differential Pulse Coded Modulation (ADPCM) algorithm. The serial arithmetic processor includes a first common circuit which is arranged to take advantage of the realization that a large portion of the LOG, FLOAT, and ANTILOG functions can be implemented in common hardware. The serial arithmetic processor further includes a second common circuit which is arranged to take advantage of the realization that large portions of the MULTIPLICATION and FLOATING POINT MULTIPLICATION functions can be implemented in other common hardware. A controller is provided for controlling logic and other circuitry in the first and second common circuits depending upon the desired function to be performed.

Abstract: A multiharmonic adaptive phase jitter compensator for a high speed modem is provided. The compensator includes an IIR filter for each harmonic of phase jitter for which compensation is desired. The coefficient update of each IIR filter as well as the input to the primary jitter frequency IIR receives identical information from a phase detector which compares an equalized phase corrected signal entering a decision means with the ideal point determined by the decision means. However, the IIRs for the higher harmonics are trained with different information. Thus, the primary jitter frequency as adaptively determined by the first IIR is fed to harmonic computation circuitry. The harmonic computation circuitry then provides an adapted second harmonic to the second harmonic IIR, and adapted third harmonic to the third harmonic IIR, etc. The outputs of all the IIRs are summed, and the cosine and sine of the sum are provided to phase correct the equalized signal before it enters the decision circuitry.

Abstract: Methods and apparatus for measuring propagation delay over a line without interfering with data communications over the line are disclosed. A known signal is sent and looped back over a secondary channel, and the loop time is measured. Because the known signal is sent at a non-interfering frequency at the edge of the passband, the loop time minus fixed delay times of the communicating means does not provide a true measure of propagation delay. Rather, the envelope delay distortion must be determined and also subtracted from the loop time. The envelope delay distortion is determined as a function of the utilized non-interfering frequency and the line length, the latter of which may be estimated from the loop time.

Abstract: A modem which is provided with the operating parameters of a plurality of countries and can be made compatible with the country in which the modem is to be used is provided.

Abstract: Methods and systems are disclosed for simultaneously measuring three impairments such as phase jitter, amplitude jitter, and noise, to a quadrature amplitude modulated data communication channel. The invention generally comprises: correlating received signals to an ideal constellation point; rotating the received signals and ideal constellation point such that the ideal point lies on the x axis; determining a phase jitter index (cos.alpha.) as a function (x/x.sub.o) of the average x coordinates of the rotated received signals and the rotated constellation point; determining an index of amplitude jitter (m.sup.2) as a function (((x.sup.2 -y.sup.2)/(2x.sub.p.sup.2 -x.sub.o.sup.2))-1) of the square of average x coordinates, the average of the square of the x coordinates, the average of the square of the y coordinates of the rotated received point, and the square of the rotated constellation point; and determining a noise index .DELTA.x.sub.n 2 as a function ((x.sup.2 +y.sup.2 -x.sub.o.sup.2 (1+m.sup.

Abstract: An intelligent synchronous modem and data communication systems utilizing the intelligent synchronous modem are provided. The modem comprises: at least one connector having a first and a second port for primary and secondary channels of communication with a host computer, wherein the primary communication channel is for communication of synchronous data and the secondary communication channel is for communication of asynchronous data; a microprocessor for recognizing and executing commands of the host computer, wherein the commands are in the form of asynchronous data received over the secondary communication channel and interface means for interfacing the microprocessor with telephone lines, wherein synchronous data received by the microprocessor is sent to the interface means.

Abstract: A bit interleaved time division multiplexer for multinode system is provided and includes a high speed bus, a plurality of aggregate common blocks, a plurality of channel common blocks, and a system controller which selects the aggregate and channel common blocks and which is connected to the bus. Each aggregate common block includes an address recognizer, a recorder for obtaining information according to a first frame format from an aggregate line, supplying an intramultiplexer system address for at least one bit of the obtained information, and sending the information accompanied by the intramultplexer system address onto the high speed bus, and a recorder and transmitter for receiving bits of information from the high speed bus, multiplexing the information according to a second frame format and sending the so-multiplexed information out over an aggregate line.

Abstract: A data communication equipment equalizer which minimizes the total training time delay (RTS-CTS) is disclosed. The total RTS-CTS delay of the provided equalizer consists of a delay due to a minimal training sequence required for the equalizer coefficients to converge given a low distortion channel, plus whatever delay is necessary for the equalizer coefficients to converge given the particular channel.

Abstract: A method is disclosed for determining with only sixty-four distance comparisions the distances between a received eight-dimensional vector comprised of four two-dimensional coordinates and each of sixteen non-overlapping subconstellations. In order to limit the comparisons, each subconstellation is represented by a collection of sixteen representational four-coordinate vectors, with each collection having four groups of vectors of the form______________________________________ (a, b, c, d) (a + 2, b + 2, c, d) (a, b, c + 2, d + 2) (a + 2, b + 2, c + 2, d + 2) ______________________________________where each letter represents in a different plane one of a set of points T(0) and its ninety, one hundred and eighty, and two hundred and seventy degree rotations, and +2 represents a one hundred and eighty degree rotation.

Abstract: The invention is a shaped base plate assembly onto which one or more separate units may be detachably mounted. One common latch plate, bolted to the base plate, fixes all the separate units in place in fixed relation to each other and to the base plate. The invention may be employed to mount four separate transformers to a common base plate. Each transformer is fitted with appendages such as four cylindrical legs, each leg being shaped with a circular undercut of reduced cross-section adjacent the free end of the leg. The base plate is formed with sets of keyhole-shape or teardrop-shape holes, with each set of holes located to accommodate the legs of a given transformer. When all four transformers have been inserted and then slid into the latched position, a latch plate is fastened by one latch screw to the base plate. The latch plate is of a shape and size to abut against at least one leg of each transformer and to bias the undercut section of each transformer leg snugly against an edge of a base plate hole.

Abstract: A current rectifier is provided and generally comprises: a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I.sub.in ; and a first current mirror with its input connected to the drain of the n-channel transistor, and its output connected to the drain of the p-channel transistor. The current rectifier preferably also includes a second current mirror with the drain of the p-channel transistor as an input to the second current mirror and the rectified output current I.sub.out as an output of the second current mirror. If an offset to the rectified current is desired, a third current mirror having a bias or offset current as an input and the output of the second current mirror as an output may be included.

Abstract: Methods for establishing and maintaining synchronization between communicating multiplexers are provided, wherein a first multiplexer having a frame format multiplexes at least data according to the frame format, and wherein the second multiplexer demultiplexes at least said data according to the frame format, and synchronization is established by: providing the frame format with bit positions for a plurality of bits including first predetermined bit positions for a plurality of checksum bits, and second predetermined bit positions for bits other than checksum bits; calculating a checksum for the bit values of bits located at said second predetermined bit positions, and inserting bits representing the said calculated checksum into said first predetermined bit positions; sending bits including bits located at said first and second predetermined bit positions in said frame format from said first multiplexer to said second multiplexer; and establishing synchronization between said first and second multiplexers b

Abstract: Methods and apparatuses for efficiently allocating bandwidth to data, control and multiplexer overhead and for providing flexible data rates and control rates are provided. The apparatuses of the invention are used in a time division miltiplexer which multiplexes for transmission over and for receipt from at least one aggregate line in accord with at least one frame, data and control information from a plurality of channels and multiplexer overhead information.

Abstract: The invention is an enclosure for containing several printed circuit boards. Detechable brackets for mounting the enclosure to a rack, detachable latching door hinges and a combination of detachable members are assembled in an improved housing for detachably enclosing mounted printed circuit boards and other modular components and includes a base, a cover having a top and depending sides provided with slots; and vertical card guide brackets and a pivotable door. These detachable members are formed so as to to latch together into an integral assembly. The door when pivoted to the open position is held as a tray in the horizontal plane of the base and does not drop below the base, with a peripheral rim of the door serving as sides of the tray.

Abstract: A bit interleaved multiplexer system permitting byte synchronization of apparatuses communicating thereon without the consumption of additional aggregate bandwidth is provided. The system comprises a multiplexer, a demultiplexer, and an aggregate line. The multiplexer includes a transmit frame which includes a memory means and at least one recirculating counter which is programmed according to a framing algorithm, and a transmit data buffer and transmit mark buffer for each terminal which is to be connected to the system. Every time the transmit frame requests a predetermined bit of a byte (e.g. an MSB), a "1" is marked in the mark buffer. When a bit leaves the mark buffer it causes the terminal to write a bit into the transmit data buffer, with the written bit being an MSB when the bit leaving the mark buffer is a "1".

Abstract: A regenerative strobe circuit for a CMOS logic gate which only dissipates energy during the strobing of the inputs into the logic array is provided. The logic gate is connected between an output node and a first voltage source. The regenerative strobe circuit includes a first transistor (P channel) which is connected between a second voltage source and the output node, a complementary inverter having P channel transistor and N channel transistor, and second and third transistors which are respectively gate controlled by a strobe signal and a signal related to the strobe signal. The second transistor (P channel) is also connected between the second voltage source and the source of the P channel transistor of the complementary inverter. The third transistor (preferably P channel) is connected to the gate of the first transistor as well as to the source of the N channel transistor of the complementary inverter.

Abstract: An A-D converter for providing the general successive rectification algorithm V.sub.out =2.vertline.V.sub.in .vertline.-V.sub.ref is disclosed. One stage of a synchronous parallel converter generally comprises a comparator, and an op amp with V.sub.in as an input to its inverting input, the noninverting input connected to ground, and the output being V.sub.out, with a first capacitor bridging the inputs of the op amp, and a second capacitor of half the capacitance of the first capacitor feeding back from the output of the op amp to its noninverting input. The location and capacitance values of the first and second capacitors perform the amplification function. Switches between the first capacitor and the op amp provide rectification, while a third capacitor between V.sub.ref and the inverting input of the op amp provides the function of subtracting V.sub.ref. Stages are cascaded such that V.sub.out of one stage is the V.sub.in of the next stage. Each stage's V.sub.