Abstract: In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an 12C data bus each coupled to a host device, a method of transferring EDID from the memory device over the 12C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Abstract: A display controller includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller, a data buffer for storing EDID read from the memory device, and an arbitration circuit for arbitrating memory device access requests between the processor and a requesting data port wherein when the data buffer is not almost empty, then the arbitration circuit grants the processor access to the memory wherein when the data buffer is almost empty, then the arbitration circuit grants only the requesting data port access to them memory so as to replenish the data buffer with read EDID.

Abstract: A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: Frequency content motion detection is performed by decomposing a raw field luminance data in to a number of frequency content sub-bands, detecting motion using the raw field luminance data in parallel with the decomposing, generating a motion correction value by multiplying absolute values of the sub-bands by weighting factors, and applying the motion correction value to detected motion.

Abstract: A method, apparatus, and system for determining a horizontal resolution and a phase of an analog video signal arranged to display a number of scan lines each formed of a number of pixels is described. A number of initialization values are set where at least one of the initialization values is a current horizontal resolution and then a difference value for each immediately adjacent ones of the pixels is determined. Next, an edge flag value based upon the difference value is stored in at least one of a number of accumulators such that when at least one of the accumulators has a stored edge flag value that is substantially greater than those stored edge flag values in the other accumulators, then the horizontal resolution is set to the current resolution.

Abstract: A method, apparatus, and system for determining a true horizontal resolution of an analog video signal arranged to display a number of features having associated feature edges on a display each of which were created with a true pixel clock is described. For a test horizontal resolution, if it is determined that substantially all of the feature edges have substantially the same phase relationship to a test pixel clock, then the test horizontal resolution is the true horizontal resolution.

Abstract: Abstract of the Disclosure In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry.

Abstract: An enumeration method for the link rate and a pixel/audio clock rate. The method can be performed by expressing the pixel/audio clock rate and the link rate with four parameters, A, B, C, and D based upon a master frequency 23.76 GHz as 210×33×57×111 Hz, and regenerating a pixel/audio clock from the link clock.

Abstract: A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.

Abstract: A memory efficient providing LC overdrive for sticky pixels at a frame n?1 for a current frame n based upon sticky pixel data associated with a frame n?2.

Abstract: Selectively providing LC overdrive by determining a relative noise level between a current video frame and a previous video frame and overdriving the current video frame based upon the determined relative noise level.

Abstract: A reduced memory method, apparatus, and system suitable for implementation in Liquid Crystal Display (LCDs) that reduces a pixel element response time thereby enabling the display of high quality fast motion images thereupon. As a method of generating an overdrive pixel value in an LCD device, a predicted pixel value is compressed and stored. The stored compressed pixel value is then retrieved and decompressed as a start pixel value. An overdrive pixel value based upon a target pixel value and the start pixel value such that the overdrive pixel value enables a pixel to reach the target pixel value within a single frame period.

Abstract: A method for reducing a response time of the pixels corresponding to a period of time required for a selected pixel at a starting pixel value to reach a target pixel value. Providing an n×n factored zero diagonal LCD overdrive matrix and for a selected pixel at a particular start pixel value, selecting a particular target pixel value to be reached in one frame time, and determining a particular overdrive pixel value based upon the particular start pixel value and the particular target pixel value using the factored zero diagonal LCD overdrive matrix. When the start pixel value and the target pixel value are equal or almost equal in value, then setting the overdrive pixel value to a main diagonal pixel value such that the start pixel value is equal to the target pixel value.

Abstract: An apparatus and method for processing Hsync and Vsync signals in graphic controllers to avoid a false reading of pulses caused by glitches. The apparatus and method involve detecting when the synch signal crosses the threshold for the first time. When this occurs, the output of the detection circuit is held for the predetermined period of time, even if subsequent transitions across threshold occur during this period. After the predetermined period expires, the output is released and may assume the same state as the input sync signal at that time. In this manner, a misinterpretation of the resolution format caused by the reading of a “false” pulse caused by a glitch on a sync signal can be avoided.

Abstract: A method of overdriving LCD panels to improve LCD pixel response time is described that does not rely upon conventional use of overdrive look up tables. The method is based upon modeling the LCD pixels as linear second-order dynamical systems that leads to simple runtime calculations requiring but a small number of stored panel specific constants.

Abstract: An extended overdrive table uses the saturation regions to store useful data that conformably extends the unsaturated region in a natural way. This extended overdrive table reduces the size of any interpolation errors when straddling crossover points to acceptable levels without requiring storing or using any crossover data. In addition, since the saturation regions are used to hold the new data, no additional storage requirements are introduced. The numeric range of the extended table is increased and it is therefore supposed that the bit depth of the table entries is increased, but the table can be resealed to retain the original bit depth with insignificant loss of accuracy. Also, the new data incorporated into the saturation regions allows run time calculation of the pixel attained at the end of the frame time that is needed as the start of the pixel for the next cycle.

Abstract: Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

Abstract: In a liquid crystal display (LCD) panel based display, a method of dynamically selecting either frame rate conversion (FRC) or pixel voltage overdrive is disclosed. The method is carried out by performing the following operations. A video vertical refresh rate of an incoming video data stream is determined and based upon the determining, only one video data stream conditioning protocol from a number of available video data stream conditioning protocols is selected. The selected video data stream condition protocol is then applied to the video data stream.