Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. A group of transfer parameters as queue entries allow code and data for an algorithm to be transferred between both local and external memory.

Abstract: A method, system and apparatus for detecting a sub-pixel pair susceptible of producing a flicker event in an image from a video signal source displayed on a liquid crystal display (LCD) unit is described. A two dimensional flicker pattern analysis is performed on a selected group of sub-pixels some of which are included in a first plurality of sub-pixels that includes a first current sub-pixel and a first next sub-pixel included in a first video frameline and a remainder of which are included in a second plurality of sub-pixels included in a second video frameline that is received, in real time, from the video signal source that includes a second current sub-pixel and a second current sub-pixel.

Abstract: A system for processing information, such as audio/video information utilized in a DVD player, can be implemented without the need for a buffer, such as a track buffer, located between the source of audio/video information and the demultiplexer which parses a packet of data. The packet of data can then be parsed into audio, video, subpicture, or navigation, portions and stored for decoding. In one embodiment, a DVD player utilizes a circuit that is synchronized to the speed of the DVD drive rather than to the speed of the decoders for each portion of data.

Abstract: A computing system comprising a host device which includes a serial communication bus and a processor for controlling communication over the serial communication bus. The computing system further comprises one or more peripheral devices connected to the communication bus. Communication between the host device and the peripheral devices is facilitated by a communication protocol, which includes a procedure for discovering whether the configuration of peripheral devices connected to the communication bus has changed. The discovery procedure starts by the host device sending a first command to all peripheral devices connected to the serial communication bus to determine if the configuration of any of the peripheral devices has changed. If a new peripheral device has been added to the communication bus, the host sends a focus command to a first comm bus port on the communication bus to focus that particular port.

Abstract: A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system. In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations [N]). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.

Abstract: A method and apparatus used to step and correct the position of raster lines in a sinusoidal or zig-zag deflection system. By combining the magnetic flux generated with a rotation “twister” coil and a vertical deflection coil, scan lines can be uniformly spaced and separated nearly to their ends. Accordingly, the magnetic flux generated with the twister coil is adjusted going in the left to right direction then reversed in polarity and readjusted while returning from right to left. It is this controlled twister flux that combines with the linear vertical deflection flux to straighten and then step each scan line to produce an aligned raster.

Abstract: A method and apparatus are provided whereby the motion between two video fields of opposite parity may be measured so as to discriminate between the presence of motion and lack thereof. The level of motion at a specified position is determined by comparing a first motion value derived from successive fields of opposite parity with a second motion value derived from successive fields of the same parity at the spatial location corresponding to that used to generate the first motion value. This determination is made with one field being common to the first and second motion values, and taking the minimum of the first and second motion values to be the motion value at that position.

Abstract: A method for measuring motion at a horizontal and vertical position between video fields of opposite parity comprising the steps of measuring the signal values of at least two vertically adjacent pixels from a video field of one parity and at least two vertically adjacent pixels from a video field of the opposite parity such that when taken together, the pixels represent contiguous samples of an image at said horizontal and vertical position, and determining whether the signal value of any of the pixels lies between the signal values of adjacent pixels in the field of opposite parity and in response outputting a zero motion value, otherwise, outputting a motion value equal to the lowest absolute difference between any of the pixels and its closest adjacent pixel in the field of opposite parity.

Abstract: A general method is provided to achieve frequency conversion in an all-digital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of time-shifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.

Abstract: A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.

Abstract: An all-digital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.

Abstract: A method and apparatus for reducing the appearance of moiré in a digitally resized image wherein each input pixel value is mapped to a new value by means of a first correction function prior to being resized. At the output of the resizing engine, each pixel in the resized image is mapped to a further new value by means of a second correction function prior to being displayed. The second correction function is chosen such that the intensity of light output from the display device is substantially proportional to the value of the signal from the resizing engine, taking into account the combined transfer functions of the second correction means and the physical display device (i.e. the second correction function is substantially the inverse of the display transfer characteristic).

Abstract: A display unit designed to be scanned within a narrow horizontal scanning range irrespective of the frequency at which the horizontal lines of an image are received. If the horizontal line frequency of the received display signal does not fall within the narrow horizontal scanning range, the image frames in the display signal are scaled at least vertically such that the number of horizontal lines in each scaled image frame times the frame rate falls within the horizontal scanning range. As a result, the images can be scanned within the horizontal range for which a display unit is designed for. The scaling can be performed without using a frame buffer as the frame rate (at which the images are encoded in a display signal) equals the scanning rate.

Abstract: A method of automatic generation of horizontal synchronization of an analog signal to a digital display is described. Accordingly, a number of features are found and for each of a range of test Htotal values, a pixel co-ordinate value for each of the found features is calculated. A pixel co-ordinate remainder value associated with each of the pixel co-ordinate values is determined and a maximum gap value of the pixel co-ordinate remainder values associated with a true horizontal resolution. is determined.

Abstract: A method, system and apparatus for synchronizing an analog video signal to an LCD monitor is described. For each of a succession of associated video frames are surveyed for a number of displayed features based upon a pseudo-random selection of regions into which the displayed video frame is divided. During successive associated video frames, a minimum number of features each is which is generated by an associated pixel clock is determined based upon a pre-selected number of scans. Subsequent to the determination of the minimum number of features, a transition region for each of plurality of horizontal resolution values is determined by scanning through a selected number of pixel clock phases. Based upon a minimum transition zone corresponding to a maximum change in the number of features for a particular pixel clock phase, an associated horizontal resolution is provided.

Abstract: A method, apparatus, and system for estimating a pixel clock associated with a video signal associated with a video frame formed of a number of pixels is described. A flat region of the video signal is detected wherein the flat region is characterized as having a slope approximately equal to zero. a central portion of the flat region is located such that the estimated pixel clock is that pixel clock corresponding to the central portion of the flat region.

Abstract: A method, apparatus, and system for determining a true horizontal resolution of an analog video signal arranged to display a number of features having associated feature edges on a display each of which were created with a true pixel clock is described. For a test horizontal resolution, if it is determined that substantially all of the feature edges have substantially the same phase relationship to a test pixel clock, then the test horizontal resolution is the true horizontal resolution.

Abstract: A programmable delay element is provided for delaying a digital input signal. The programmable delay element comprises a discharge capacitor adapted to be precharged to a predetermined voltage in response to a first transition of the digital input signal. A transistor switch of a first type is provided for precharging the discharge capacitor to a predetermined voltage. A discharge current source is connected via a sense node to the discharge capacitor for discharging the capacitor in response to a subsequent opposite transition of the digital input signal. A transistor switch of a second type is provided for connecting the discharge capacitor to the discharge current source and thereby discharging the discharge capacitor. A reference voltage source is provided for applying a reference voltage to a reference node.

Abstract: A digital display unit adjusting the phase of a sampling clock based on the examination of a display data signal contained in a received analog display signal. The phase may be adjusted by determining a boundary between display data portions representing successive pixel data elements. As the boundaries provide the timing information related to the source clock, the phase of the sampling clock can be adjusted when ever the boundaries can be determined accurately. The phase of the sampling clock can be adjusted potentially every sampling clock cycle if the boundaries can be determined. The area for examination can be minimized by first determining an expected boundary based on synchronization signal accompanying the analog display data, and examining only a small area surrounding the expected boundary.

Abstract: A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.