Abstract: The disclosure provides a USB device, a USB cable, and a USB repeater. The USB cable or the USB device includes a USB connector and the USB repeater. The USB repeater may gain a signal of a differential pin pair of the USB connector. The USB repeater may monitor a signal of a configuration channel pin of the USB connector. The USB repeater selectively runs in one of a plurality of working modes corresponding to a plurality of protocols according to a monitoring result.

Abstract: An apparatus and a method of implementing activation logic for a neural network are described. The apparatus comprises an input unit, a first address translated look-up table, an intermediate storage unit, a second address translated look-up table, and an output unit. The first address translated look-up table includes (2{circumflex over (?)}n1) first entries that map to (2{circumflex over (?)}n1) addresses based on the n bits of the input unit. Each the (2{circumflex over (?)}n1) first entries includes (n1?1) first preset values. The intermediate storage unit includes (n?1) bits. The second address translated look-up table includes (2{circumflex over (?)}(n?1)) second entries that map to the (2{circumflex over (?)}(n?1)) bit addresses based on of the (n?1) bits of the intermediate storage unit. Each the (2{circumflex over (?)}(n?1)) second entries includes (n2+1) second preset values.

Abstract: A data processing method, a multichip system, and a non-transitory computer-readable medium for implementing a neuron network application are provided. The data processing method includes: allocating corresponding chips to process a corresponding part of a first stage data and a corresponding part of a second stage data; transmitting, by a first chip, a first part of the first stage data to a second chip through a channel; transmitting, by the second chip, a second part of the first stage data to the first chip through the channel; computing, by the first chip, the first stage data with a first part of weight values to obtain a first result, and computing, by the second chip, the first stage data with a second part of weight values to obtain a second result, where the first result and the second result are one of the second stage data.

Abstract: The present invention provides a power supply controlling module, which is suitable for a power supply controlling device. The power supply controlling device comprises a power source and a plurality of connecting ports. The power supply controlling module comprises a plurality of control units and a resistance. Each of the control units respectively connects with each of the connecting ports. The control units comprise a first control unit and at least one second control unit. The resistance electrically connects with the control units. The first control unit comprises a detecting circuit and a first control circuit, which respectively connects with the resistance. Each of the at least one second control unit comprises a second control circuit, which respectively connects with the resistance.

Abstract: A universal serial bus (USB) hub for connecting different port types and method thereof are provided. In one embodiment, USB controller detects the power level of each dynamic port to determine whether one of the dynamic ports is connected to the host device wherein the connected dynamic port is defined as upstream port. The disconnected dynamic port of the dynamic ports is defined as downstream port to be connected to the peripheral device. In another embodiment, the USB controller selectively disables the disconnected dynamic port of the dynamic ports. The present invention improves the application flexibility of connecting wire between the hub and the host device.

Abstract: A system for detecting universal serial bus (USB) device and method thereof are described. The system and method utilizes a USB controller to control a switch module and to detect the signal level of USB interface for determining whether the USB device is electrically connected to the host unit. Therefore, the system and method are capable of improving the power consumption of the host unit.

Abstract: A universal serial bus controller and host are adapted for being electrically connected to a universal serial bus device. The universal serial bus host includes: a wiring substrate including a plurality of first substrate contacts and a plurality of second substrate contacts; a universal serial bus connecting port disposed on the wiring substrate via the first substrate contacts; and the universal serial bus controller including a plurality of pins electrically connected to the wiring substrate via the second substrate contacts. The universal serial bus controller and the host can decrease interferences among signals and avoid the complicated layout of the wiring substrate.

Abstract: A junction box for connecting a power supply unit is disclosed. The junction box includes a first connection terminal, a second connection terminal, a first signal connection terminal, a second signal connection terminal, and a switching module. The first and second connection terminals are utilized to transmit a DC power provided by the power supply unit. The first and second signal connection terminals are utilized to transmit a control signal. The switching module controls the electrically coupling relationship between the first connection terminal and the second terminal according to the control signal. A power system which employs the junction boxes and a method for controlling the power system are also disclosed.

Abstract: A transceiver system having a phase and frequency locked architecture is described. The transceiver system includes a clock and data recovery type receiver, a frequency divider and a transmitter. The clock and data recovery type receiver receives an external signal from a host unit and extracts the external signal to generate a clock signal and a data signal. The frequency divider is used to divide the frequency of the clock signal for generating a reference clock signal. The transmitter transmits output data content based on the reference clock signal.

Abstract: A flash memory system and managing and collecting methods for flash memory with invalid page messages thereof are described. When the valid data pages of the flash memory are changed to invalid data pages, a recording area is used to record the message of the invalid data pages to effectively collect the occupied space of the invalid data pages in the flash memory. Further, while garbage collecting step is performed, a block is rapidly selected according to the message of the recording area and the valid data pages in the selected block are correctly identified, copied and removed.

Abstract: A method for processing image data is described. The method includes the steps: (a) fully writing image data into first buffer area; (b) vertically reading the image data in first buffer area and horizontally writing image data into second buffer area; (c) while completely reading a first portion of first buffer area, allocating the complete read first portion of first buffer area to second buffer area to be served as a writing section; (d) vertically reading the image data in a second portion of first buffer area and writing the image data into second buffer area; and (e) vertically reading the image data of second buffer area and horizontally writing the image data into first buffer area, and after completely reading a portion of second buffer area, allocating the read portion of second buffer area to first buffer area.

Abstract: A junction box for connecting a power supply unit is disclosed. The junction box includes a first connection terminal, a second connection terminal, a serial carrier interface module, and a control module. The first connection terminal and the second terminal are utilized to connect the junction box and another junction box in a serial connection. The serial carrier interface module is electrically coupled to the first connection terminal and the second connection terminal for the transmission of a carrier and a DC power, which is provided from the power supply unit. The control module is electrically coupled to the serial carrier interface module for receiving the carrier and for controlling of the transmission of the DC power according to the carrier. A power system which employs the junction boxes and a method for controlling the power system are also disclosed.

Abstract: A dynamic power management system for USB hub and method thereof are described. The dynamic power management system includes a host device, a power unit and a hub device. A power management module disposed in the hub device dynamically adjusts the power-supplying statuses of ports in the hub device and further reduces the cost of power transformer externally connected to the hub device.

Abstract: A data access system, device and controller are provided. The data access system includes a plurality of storage units and first controllers, a second controller, and a host. The first controller is utilized to parallel access the storage units, and each first controller includes a plurality of first storage unit controllers, a buffer and a multiplexer. The first storage unit controllers are coupled one-to-one with the storage units. The multiplexer is coupled to the first storage unit controllers and the buffer. The second controller is coupled to the first controllers. The second controller includes a plurality of second storage unit controllers which are coupled one-to-one with the first controllers. The host is coupled to the second controller, and accesses the storage units through the second controller and the first controllers.

Abstract: A detection method of low frequency handshaking signal is described. The method includes the following steps of: (a) performing first impedance calibration when host device is activated for sending a first low frequency signal based on the first impedance calibration and performing a second impedance calibration when a controlled device is activated for sending a second low frequency signal based on the second impedance calibration; (b) transmitting a first high frequency training signal from the host device to the second receiver of the controlled device when the first low frequency signal and the second low frequency signal are in a predetermined condition; and (c) transmitting a second high frequency training signal from the controlled device to the first receiver of the host device wherein the frequency of the first low frequency signal and the second low frequency signal is smaller than the frequency of the first high frequency training signal and the second high frequency training signal.

Abstract: A light compensation scheme, an optical machine device, a display system and a method for light compensation are disclosed herein. The light compensation scheme includes a detector for inspecting a data related to a luminous flux of each of different color beams, and a controller for selectively adjusting anytime a luminosity of at least one of a plurality of pointolites and/or the transmittances of at least one part of liquid crystals disposed within a liquid crystal display panel, based on the inspected data.

Abstract: A USB charging system and the method thereof are disclosed. The USB charging system includes a hub device having a charging function module and a plurality of connection ports. The charging function module dynamically distributes the charging current to the connection ports based on power supply ability of a power unit for providing the charging current to at least one chargeable device wherein the charging current is greater than USB protocol current.

Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.

Abstract: A method for processing image data is described. The method includes the steps: (a) fully writing image data into first buffer area; (b) vertically reading the image data in first buffer area and horizontally writing image data into second buffer area; (c) while completely reading a first portion of first buffer area, allocating the complete read first portion of first buffer area to second buffer area to be served as a writing section; (d) vertically reading the image data in a second portion of first buffer area and writing the image data into second buffer area; and (e) vertically reading the image data of second buffer area and horizontally writing the image data into first buffer area, and after completely reading a portion of second buffer area, allocating the read portion of second buffer area to first buffer area.

Abstract: A transceiver system having a phase and frequency locked architecture is described. The transceiver system includes a clock and data recovery type receiver, a frequency divider and a transmitter. The clock and data recovery type receiver receives an external signal from a host unit and extracts the external signal to generate a clock signal and a data signal. The frequency divider is used to divide the frequency of the clock signal for generating a reference clock signal. The transmitter transmits output data content based on the reference clock signal.