Abstract: A non-volatile memory includes a plurality of blocks and a controller. Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages includes a plurality of storage units. The controller is configured to perform: receiving an erase command for a target block of the plurality of blocks; executing a read operation on each page of the target block; and executing a first erase operation to apply word line voltages to the plurality of pages, where the word line voltages are determined by a read result of the read operation of each page. An operation method of a non-volatile memory and an electronic device are also provided.

Abstract: A non-volatile memory includes: a plurality of word lines; a plurality of bit lines; a plurality of pages; and a controller. Each of the plurality of pages includes a plurality of data storage units and at least one flag storage unit. The controller is configured to perform: writing a data stream into the plurality of data storage units; setting a flag in response to a number of bits “0” in the data stream and a number of bits “1” in the data stream; and writing the flag into the plurality of flag storage units, where the flag indicates whether the data stream is inversed. A writing method and a reading method of a non-volatile memory are also provided.

Abstract: A non-volatile memory includes: a plurality of user data storage blocks configured to store user data; a user setting storage block configured to store a bad block address table; and a controller configured to perform: executing a first erase operation on one of the plurality of user data storage blocks according to an external instruction; executing a second erase operation on the one of the plurality of user data storage blocks in response to failure of the first erase operation; marking the one of the plurality of user data storage blocks as a bad block in response to failure of the second erase operation; and updating the bad block address table stored in the user setting storage block according to the bad block newly marked. An operation method of the non-volatile memory is also provided.

Abstract: An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

Abstract: Provided are a flash memory and an operation method thereof. The flash memory includes a memory cell array, a controller and a register. The register stores read parameters that include a read voltage value and a read pass voltage value. The controller is configured to perform the read operation on a selected page according to the read parameters to read out the raw data stored in the selected page, determine whether the raw data includes an error bit, and in response to determining that the raw data includes the error bit, update the read parameters by decreasing the read voltage value and/or increasing the read pass voltage value.

Abstract: Disclosed are a nonvolatile memory and an operation method thereof. The nonvolatile memory includes a memory cell array and a controller. The controller is configured to: read out raw data from a plurality of memory cells in the memory cell array; correct the raw data by using error correction code (ECC) data to obtain corrected data; determine an address of a memory cell having a data loss error in the plurality of memory cells; and program the memory cell having the data loss error. After the ECC correction in the read operation, the data loss error is corrected by a program operation.

Abstract: Provided are a mode conversion method and a mode conversion apparatus for a nonvolatile memory. The method includes: receiving a first user command that is sent by an upper computer and belongs to a user mode, where the first user command includes an invoking path disabling instruction; sending an enable signal according to the invoking path disabling instruction; and disabling the module path for controlling the high-bit I/O ports [15:8] in the X16 nonvolatile memory according to the enable signal. After the module path for controlling the high-bit I/O ports [15:8] in the nonvolatile memory is disabled, data transmission and reception of the nonvolatile memory are implemented through the low-bit I/O ports [7:0], and the X16 nonvolatile memory is converted into an X8 mode.

Abstract: A nonvolatile memory includes: a memory cell array having a first portion and a second portion, a temperature sensor configured to measure a temperature of the memory cell array, and a controller. The first portion is programmable, readable and erasable to a predefined user, and the second portion is not programmable and erasable to the predefined user. The controller is configured to: perform an operation in the first portion in response to an instruction of the purchaser, and in response to determining that a predetermined condition is satisfied, write the temperature of the memory cell array when doing the operation and operation information related to the operation into the second portion.

Abstract: Disclosed are a nonvolatile memory and a programming method to reduce the tunnel oxide stress. The programming method includes: applying one program voltage pulse to a word line connected to a target memory cell, and then applying one or more incremental step voltage pulses to the word line connected to the target memory cell. The one program voltage pulse linearly increases from a first voltage level to a second voltage level, or the one program voltage pulse is in a staircase shape. The one or more incremental step voltage pulses start from an initial voltage level and have a predetermined step size.

Abstract: An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.

Abstract: The present application provides a NAND flash memory, comprising: a control unit, which includes a signal receiving unit, a voltage boosted circuit and a flash array; and a power source supplying power to the control unit; wherein when the voltage boosted circuit receives an erase signal from the signal receiving unit, the voltage boosted circuit exerts a device erase pulse whose magnitude is larger than an initial voltage to blocks of the flash array to permanently erase data in the blocks; the blocks include power-on read blocks. By removing data from at least power-on read blocks, the present invention discloses a scheme for permanently destroying the NAND flash memory.

Abstract: A NAND flash memory including a control unit which includes a signal receiving circuit and a flash array; the signal receiving circuit is used to receive a cache read command from an external NAND controller; the flash array includes at least one chip, each chip includes at least one plane, each plane includes a plurality of blocks, each block includes a plurality of pages; when a cache read command is received, it reads pages in a first block according to an address of the page until reaching the last page in the first block; when the last page in the first block is reached, an address of a next to-be-read page is generated according to an address of the last page in the first block to allow the cache read command to read the next to-be-read page.

Abstract: Provided are a programming method, programming apparatus and storage medium to reduce threshold voltage distribution in a non-volatile memory. The method includes performing program loops on a target page by sequentially using first programming voltages Vn; and when a predetermined condition is reached, proceeding to perform program loops on the target page by sequentially using second programming voltages Um until the target page is successfully programmed. Vn=V1+(n?1)×d1, where n denotes a program loop count of the first programming voltages, n is an integer greater than or equal to 1, and V1 and d1 are all positive numbers. Um=Vn+(m?1)×d2, where m denotes a program loop count of the second programming voltages, m is an integer greater than or equal to 2, and d2 is a positive number not equal to d1.

Abstract: The present application provides a NAND flash memory with wordline voltage compensate, including wordlines. Each wordline corresponds to a wordline voltage with a compensated temperature coefficient. The wordlines are divided into a plurality of groups, each group corresponds to a compensated temperature coefficient. Each wordline corresponds to a wordline address, and the groups of wordlines are divided by at least a border according to wordline addresses, or divided by zones having fixed number of wordlines.

Abstract: The present application provides a NAND flash memory and a method for indicating program status of wordline in a NAND flash memory, the NAND flash memory comprises: a wordline including a plurality of columns, the columns include NOP columns, which are used to store NOP bytes, one of the NOP bytes is programmed after the wordline is programmed for one time. The method includes: performing program operation to a wordline; and after the wordline is programmed for one time, programming one of NOP bytes; if all the NOP bytes are programmed, outputting a NOP status. The present application could effectively prevent the error occurs due to over-time programming the same wordline.

Abstract: Methods, systems, and machine-readable storage medium for programming a storage device are disclosed. In some embodiments, the methods include: performing a verify operation on a plurality of storage elements of the storage device to determine whether the plurality of storage elements have been programmed to a first program state; determining a first number of failing bits corresponding to the first program state based on the verify operation; comparing the first number of failing bits with a first threshold of failing bits corresponding to the first program state; and determining a second threshold of failing bits based at least in part on the first number of failing bits and the comparison, wherein the second threshold of failing bits corresponds to a second program state.

Abstract: A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.

Abstract: The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.

Abstract: A NAND flash memory including a plurality of levels of cells and a plurality of bitlines. Each bitline corresponds to a plurality of program states, the program states include an Erase-state, a highest state and a plurality of middle states, wherein the bitline voltages of the middle states during programming are between the bitline voltage of the Erase-state and the bitline voltage of the highest state during programming, and the bitline voltages of the middle states during programming are different from each other. The bitline program voltages of middle states of a NAND flash memory are controlled, thus a higher initial programming voltage of wordlines can be set without causing over-programming on the middle states of the bitlines. Therefore, program time is saved, and the programming speed is increased to achieve a fast program function.

Abstract: The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining, whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.