Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Abstract: A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock.

Abstract: A register system includes a register unit and a control unit. The register unit is utilized for storing a first data packet, wherein the register unit has an end flag. The control unit is coupled to the register unit, for indicating a designated information and an end position of the first data packet by using the end flag.

Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.

Abstract: A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Abstract: A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.

Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.

Abstract: A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal according to a control signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock.

Abstract: A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: For a negative-powered IC, an ESD protection circuit includes a negative voltage clamping circuit configured to provide a path for discharging ESD transient currents associated with different negative power supplies of the IC.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive.