Abstract: A delay locked loop (DLL) circuit for improving jitters includes a detecting unit, a master controller, a slave controller, first and second variable delay lines, first and second dummy loads, and a processor. The master controller generates a first control signal in response to a detecting signal. The slave controller generates a second control signal in response to the detecting signal. The first variable delay line delays a reference clock in response to the first control signal so as to generate a delay clock. The processor is configured to selectively generate a slave input signal, wherein if the processor does not generate the slave input signal, the processor makes the second dummy load draw a load current from the slave controller.

Abstract: In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.

Abstract: Circuits and methods for providing control of a power up sequence for supplying a gated power supply to a circuit portion. A power switch fabric is provided having more than two chains with more than two bits of control. The chains include power switches that are sequentially enabled in response to control signal to supply a virtual power supply to a gated circuit to support power gating. The power switches may include daughter switches and mother switches, where the mother switches are enabled later in time than the daughter switches. The enable signals to allow the virtual power supply to begin powering up may be timed to control the ramp up time, in rush current and peak current during the power up sequence of the virtual power supply. Methods for providing timing for the daughter and mother switches and enables to multiple chains in a power switch fabric are disclosed.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract: In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop.

Abstract: In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract: For a multi-powered IC, an ESD protection circuit includes multiple voltage clamping circuits, each configured to provide a path for discharging an ESD transient current associated with a corresponding power supply.

Abstract: For a negative-powered IC, an ESD protection circuit includes a negative voltage clamping circuit configured to provide a path for discharging ESD transient currents associated with different negative power supplies of the IC.

Abstract: In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition.

Abstract: A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.

Abstract: In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage.

Abstract: In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop.

Abstract: In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an output coupled to a second power domain, and a hold enable input, wherein the memory element is configured to hold an input state when the hold enable input becomes asserted.

Abstract: System and method for digitally watermarking data. A preferred embodiment comprises a quantizer to limit a data value provided by a signal input to a set of values, a rounder unit coupled to the quantizer, a control unit coupled to the rounder unit and to a watermark input, and a multiplexer having a first input coupled to the rounder unit and a control input coupled to the control unit. The rounder unit rounds a quantized data value to a nearest integer, the control unit provides a control signal based on the rounded, quantized data value and a parity of a watermark provided by the watermark input, and the multiplexer selects between an output of the rounder unit, an incremented output of the counter unit, and a decremented output of the counter unit, based on the control signal provided by the control unit.

Abstract: System and method for memory efficient decode and viewing of compressed image files. A preferred embodiment comprises a decoder coupled to a data input, a resize unit coupled to the decoder, a memory coupled to the resize unit, and a reorder data unit coupled to the memory. The decoder decompresses image data that is provided by the data input, while the resize unit resizes the decompressed image data from a first size to a second size. The memory stores the resized image data and the reorder data unit rearranges the image data into a format suitable for display. By resizing the image data prior to subsequent processing, memory requirements (such as storage space and bandwidth) are reduced.

Abstract: A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and the current mirror for charging a capacitor when a voltage thereof is lower than a predetermined threshold voltage and for discharging the capacitor when the voltage thereof is higher than the predetermined threshold voltage, thereby generating a clock signal at a predetermined frequency, wherein the charge control module adjusts the predetermined frequency by changing the predetermined threshold voltage.