Patents Assigned to GLOBALWAFERS CO., LTD.
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Patent number: 12336212Abstract: An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (?m) and satisfies Y?(0.2171)ln(X)?8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.Type: GrantFiled: November 17, 2022Date of Patent: June 17, 2025Assignee: GLOBALWAFERS CO., LTD.Inventors: Po-Jung Lin, Jia-Zhe Liu
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Patent number: 12224322Abstract: An epitaxial structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a diffusion barrier layer, and a P-type gallium nitride layer sequentially stacked from bottom to top. The P-type gallium nitride layer has a first lattice constant. The diffusion barrier layer includes a chemical composition of Inx1Aly1Gaz1N, where x1+y1+z1=1, 0?x1?0.3, 0?y1?1.0, and 0?z1?1.0. The chemical composition of the diffusion barrier layer has a proportional relationship so that the diffusion barrier layer has a second lattice constant that matches the first lattice constant, and the second lattice constant is between 80% and 120% of the first lattice constant.Type: GrantFiled: April 23, 2021Date of Patent: February 11, 2025Assignee: GLOBALWAFERS CO., LTD.Inventors: Tzu-Yao Lin, Jia-Zhe Liu, Ying-Ru Shih
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Publication number: 20240304442Abstract: A method of fabricating an epitaxial structure includes providing a silicon carbide substrate and placing the silicon carbide substrate in a growth chamber; forming a nucleation layer on a surface of the silicon carbide substrate, wherein a process gas required to grow the nucleation layer includes a first gas; a process of growing the nucleation layer includes performing a growth step; the growth step includes performing a first action and then performing a second action; the first action includes introducing the first gas into the growth chamber; the second action includes stopping introducing the first gas into the growth chamber; the growth step is repeated a plurality of times to form the nucleation layer; and forming a nitride epitaxial layer on a surface of the nucleation layer.Type: ApplicationFiled: January 25, 2024Publication date: September 12, 2024Applicant: GLOBALWAFERS CO., LTD.Inventor: PO-JUNG LIN
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Patent number: 12076677Abstract: A method for collecting dust from a single crystal growth system includes providing dry air and oxygen into an exit pipe connecting to the single crystal growth system, blowing a first inert gas into the exit pipe to compel the dust oxide toward a dust collecting device, collecting the dust oxide by the dust collecting device; and providing a rotary pump to transport residues of the dust oxide backward. The oxygen reacts with the unstable dust for forming dust oxide. The exit pipe is used to exhaust unstable dust from the single crystal growth system.Type: GrantFiled: July 3, 2023Date of Patent: September 3, 2024Assignee: GLOBALWAFERS CO., LTD.Inventors: Masami Nakanishi, Yu-Sheng Su, I-Ching Li
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Publication number: 20240249969Abstract: A wafer carrier with a bottom for connecting to a shaft includes a disc body and at least one heat insulator. The disc body has an accommodating groove for accommodating a wafer, and the disc body has a first surface and a second surface opposing each other. A groove bottom of the accommodating groove has the first surface. The at least one heat insulator is disposed on either the first surface or the second surface. When the wafer is accommodated in the accommodating groove, the at least one heat insulator is positioned between the wafer and the shaft.Type: ApplicationFiled: January 16, 2024Publication date: July 25, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: CHIH-YUAN CHUANG, JUI-PIN CHEN, JIA-ZHE LIU
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Patent number: 12037698Abstract: Methods for growing single crystal silicon ingots that involve silicon feed tube inert gas control are disclosed. Ingot puller apparatus that include a flange that extends radially from a silicon funnel or from a silicon feed tube to reduce backflow of gases from the silicon feed tube into the growth chamber are also disclosed.Type: GrantFiled: January 6, 2022Date of Patent: July 16, 2024Assignee: GLOBALWAFERS CO., LTDInventors: Matteo Pannocchia, Maria Porrini
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Patent number: 12006589Abstract: A purification apparatus and a method of purifying hot zone parts are provided. The purification apparatus is configured to remove impurities attached on at least one hot zone part. The purification apparatus includes a crystal high temperature furnace, an enclosed box disposed in the crystal high temperature furnace, an outer tube connected to the crystal high temperature furnace and the enclosed box, an inner tube disposed in the outer tube, and a gas inlet cover connected to the outer tube. The crystal high temperature furnace includes a furnace body, a furnace cover, and a thermal field module disposed in the furnace body. The gas inlet cover is configured to input a noble gas into the enclosed box through the inner tube, and the thermal field module is configured to heat the noble gas so that the impurities are heated and vaporized through the noble gas.Type: GrantFiled: February 24, 2022Date of Patent: June 11, 2024Assignee: GLOBALWAFERS CO., LTD.Inventors: Chung-Sheng Chang, Masami Nakanishi, Yu-Sheng Su, Yen-Hsun Chu, Yung-Chi Wu, Yi-Hua Fan
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Publication number: 20240170564Abstract: An epitaxial structure includes a substrate, a first buffer layer, a second buffer layer, and a channel layer, wherein the first buffer layer is located on a top of the substrate and includes a first portion. The first portion includes a nitride, which is ternary and above, and an aluminum atom concentration of the first portion is less than or equal to 25 at %. The first portion has an element doping, wherein a doping concentration of the element doping of the first portion is greater than or equal to 1×1018 cm?3. The second buffer layer is located on a top of the first buffer layer. The second buffer layer is provided without aluminum and has an element doping. The channel layer is located on a top of the second buffer layer.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, JIA-ZHE LIU, HONG-CHE LIN, CHIH-YUAN CHUANG
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Patent number: 11982019Abstract: A crystal growth doping apparatus and a crystal growth doping method are provided. The crystal growth doping apparatus includes a crystal growth furnace and a doping device that includes a feeding tube inserted to the furnace body along an oblique insertion direction, and a storage cover and a gate tube that are disposed in the feeding tube. The feeding tube extends from an outer surface thereof to form a placement opening, and the placement opening is recessed from an edge thereof to form an upper recessed portion and a lower recessed portion along the oblique insertion direction. The storage cover includes a storage tank and a handle. When the storage cover is disposed in the gate tube body, the gate tube body is configured to isolate an inner space of the feeding tube from the placement opening.Type: GrantFiled: May 27, 2022Date of Patent: May 14, 2024Assignee: GLOBALWAFERS CO., LTD.Inventors: Yu-Chih Chu, Tang-Chi Lin, Han-Sheng Wu, Hsien-Ta Tseng
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Patent number: 11952676Abstract: A silicon carbide crystal includes a seed layer, a bulk layer and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.Type: GrantFiled: October 16, 2020Date of Patent: April 9, 2024Assignee: GLOBALWAFERS CO., LTD.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
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Patent number: 11923454Abstract: An epitaxial structure includes a substrate, a lower super-lattice laminate, a middle super-lattice laminate, an upper super-lattice laminate and a channel layer. The lower super-lattice laminate includes a plurality of first lower film layers and a plurality of second lower film layers stacked alternately. The first lower film layer includes aluminum nitride. The second lower film layer includes aluminum gallium nitride. The middle super-lattice laminate includes a plurality of first middle film layers and a plurality of second middle film layers stacked alternately. The first middle film layer includes aluminum nitride. The second middle film layer includes gallium nitride doped with a doping material. The upper super-lattice laminate includes a plurality of first upper film layers and a plurality of second upper film layers stacked alternately. The first upper film layer includes gallium nitride doped with the doping material. The second upper film layer includes gallium nitride.Type: GrantFiled: April 23, 2021Date of Patent: March 5, 2024Assignee: GLOBALWAFERS CO., LTD.Inventors: Wei-Jie Sie, Jia-Zhe Liu, Ying-Ru Shih
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Publication number: 20240063291Abstract: A method for epitaxy of a high electron mobility transistor includes: provide a substrate; form a nucleation layer on the substrate; form a buffer layer on the nucleation layer; form a first nitride layer being in contact with the buffer layer on the buffer layer; form a second nitride layer being in contact with the first nitride layer on the first nitride layer, and perform carbon doping on the second nitride layer; form a channel layer on the second nitride layer; and form a barrier layer on the channel layer; a two-dimensional electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer; a growth temperature of the second nitride layer is less than a growth temperature of the first nitride layer; a film thickness of the first nitride layer is less than a film thickness of the second nitride layer.Type: ApplicationFiled: June 22, 2023Publication date: February 22, 2024Applicant: GLOBALWAFERS CO., LTD.Inventor: JIA-ZHE LIU
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Publication number: 20240063329Abstract: A method of manufacturing a light-emitting element, including: provide a substrate; form a nucleation layer above the substrate; form a buffer layer above the nucleation layer; form a first nitride layer being in contact with the buffer layer above the buffer layer; form a second nitride layer being in contact with the first nitride layer above the first nitride layer; form a first semiconductor layer above the second nitride layer; form a light-emitting layer above the first semiconductor layer; form a second semiconductor layer above the light-emitting layer. The light-emitting layer is adapted to emit light when electrons and holes recombine. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer, and a growth pressure of the first nitride layer is smaller than a growth pressure of the second nitride layer.Type: ApplicationFiled: August 1, 2023Publication date: February 22, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: JIA-ZHE LIU, CHIH-YUAN CHUANG
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Publication number: 20240063270Abstract: A high electron mobility transistor epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a first nitride layer, a second nitride layer, a channel layer, and a barrier layer. The nucleation layer is located above the substrate. The buffer layer is located above the nucleation layer. The first nitride layer is located above the buffer layer and is in contact with the buffer layer. The second nitride layer is located above the first nitride layer and is in contact with the first nitride layer. A film thickness of the first nitride layer is less than a film thickness of the second nitride layer. The second nitride layer is carbon doped. A carbon concentration of the first nitride layer is less than a carbon concentration of the second nitride layer. The channel layer is located above the second nitride layer.Type: ApplicationFiled: June 22, 2023Publication date: February 22, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: JIA-ZHE LIU, HONG-CHE LIN
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Publication number: 20240063335Abstract: A light-emitting element structure includes a substrate, a nucleation layer located above the substrate, a buffer layer located above the nucleation layer, a first nitride layer located above the buffer layer and being in contact with the buffer layer, a second nitride layer located above the first nitride layer and being in contact with the first nitride layer, a first semiconductor layer located above the second nitride layer, a light-emitting layer, and a second semiconductor layer located above the light-emitting layer. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer. A dislocation defect density of the second nitride layer is smaller than or equal to 3×109 cm?2. The light-emitting layer is located above the first semiconductor layer and is adapted to emit light when electrons and holes recombine.Type: ApplicationFiled: August 1, 2023Publication date: February 22, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: JIA-ZHE LIU, PO-JUNG LIN
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Publication number: 20230369447Abstract: A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.Type: ApplicationFiled: April 3, 2023Publication date: November 16, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: JIA-ZHE LIU, TZU-YAO LIN
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Publication number: 20230360909Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face having an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer having a thickness less than 50 nm on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230360910Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face, and the growth face has an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230357916Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon nitride (SiC) substrate having a carbon face (C-face) without an off-angle; B: form an amorphous structure layer on the C-face of the SiC substrate; C: deposit a first group III nitride layer on the amorphous structure layer; and D: deposit a second group III nitride layer on the first group III nitride layer. By forming the amorphous structure layer, a top surface of the second group III nitride layer could be made to be in a flat and smooth state.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230290873Abstract: An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×1015 cm?3.Type: ApplicationFiled: November 17, 2022Publication date: September 14, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, JIA-ZHE LIU