Abstract: Cleave systems for separating bonded wafer structures, mountable cleave monitoring systems and methods for separating bonded wafer structures are disclosed. In some embodiments, the sound emitted from a bonded wafer structure is sensed during cleaving and a metric related to an attribute of the cleave is generated. The generated metric may be used for quality control and/or to adjust a cleave control parameter to improve the quality of the cleave of subsequently cleaved bonded wafer structures.

Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

Abstract: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

Abstract: Provided is a semiconductor epitaxial structure including a nucleation layer disposed on a substrate; a buffer layer disposed on the nucleation layer; a semiconductor layer disposed on the buffer layer; a barrier layer disposed on the semiconductor layer; and a cap layer disposed on the barrier layer. In a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/?30 ?m, a maximum value or a minimum value of a ratio of a thickness of the buffer layer to a thickness of the semiconductor layer is represented as following formula: Y=aX1?bX2+cX3, X1?0 nm, X2?750 nm, X3?515 nm, wherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is a ratio of X3 to X2.

Abstract: A method of counting sheet materials applied to a pile of sheet materials, comprising the steps of: receiving an image of the pile of sheet materials; obtaining a grayscale value of a plurality of pixels along a first image axis direction of the image to form an one dimensional first array; performing binarization of the first elements of the first array with a first threshold value to form an one dimensional second array; obtaining the number of the second elements of a first value appearing between two second elements of a second value in the second array to form a third array; dividing the elements of the third array into a first cluster and a second cluster with a second threshold value; counting the number of the third elements belonging to the first cluster and defining said number as the number of the first sheet materials.

Abstract: A crystal pulling apparatus for producing an ingot is provided. The apparatus includes a furnace and a gas doping system. The furnace includes a crucible for holding a melt. The gas doping system includes a feeding tube, an evaporation receptacle, and a fluid flow restrictor. The feeding tube is positioned within the furnace, and includes at least one feeding tube sidewall, a first end through which a solid dopant is introduced into the feeding tube, and an opening opposite the first end through which a gaseous dopant is introduced into the furnace. The evaporation receptacle is configured to vaporize the dopant therein, and is disposed near the opening of the feeding tube. The fluid flow restrictor is configured to permit the passage of solid dopant therethrough and restrict the flow of gaseous dopant therethrough, and is disposed within the feeding tube between the first end and the evaporation receptacle.

Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Abstract: A silicon carbide crystal and a method for manufacturing the same are disclosed. The silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low concentration. Therefore, the crystal defects can be significantly reduced.

Abstract: A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

Abstract: Systems and methods for processing semiconductor structures are provided. The methods generally include determining a desired removal map profile for a device layer of a semiconductor structure, determining a set of process parameters for use in an epitaxial smoothing process based on the desired removal map profile, and selectively removing material from the device layer by performing an epitaxial smoothing process on an outer surface of the device layer.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method for preparing semiconductor on insulator structures comprises transferring a thin layer of silicon from a donor substrate onto a handle substrate.

Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.

Abstract: Methods for forming single crystal silicon ingots with improved resistivity control. The methods involve growth and resistivity measurement of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The resistivity of the sample rod may be measured directly by contacting a resistivity probe with a planar segment formed on the sample rod. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and comprises a region of nitrogen-reacted nanovoids in the front surface region; a silicon dioxide layer on the surface of the semiconductor handle substrate; a dielectric layer in contact with the silicon dioxide layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

Abstract: Methods for forming single crystal silicon ingots with improved resistivity control. The methods involve growth and resistivity measurement of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The resistivity of the sample rod may be measured directly by contacting a resistivity probe with a planar segment formed on the sample rod. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a transistor and a heat dissipation structure. The substrate includes first and second semiconductor layers, and includes an insulating layer disposed between the first and second semiconductor layers. The substrate has a recess extending into the insulating layer from a surface of the first semiconductor layer. The transistor includes a hetero-junction structure, a gate electrode, a drain electrode and a source electrode. The hetero-junction structure is disposed on the second semiconductor layer. The gate, drain and source electrodes are disposed over the hetero-junction structure. The gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure located between the drain electrode and the source electrode is overlapped with the recess of the substrate.