Abstract: In an X-ROM memory device both metal changeable GND lines and polysilicon changeable GND lines are used as a changeable GND line. The metal changeable GND lines are respectively located on both sides of an array of a fixed number of polysilicon changeable GND lines. Odd polysilicon changeable GND lines are commonly connected to one metal changeable GND line through a predetermined polysilicon line, and even polysilicon changeable GND lines are commonly connected to the other metal changeable GND line through another predetermined polysilicon line. Each of the metal changeable GND lines are then connected to a GND terminal through the driving cell transistors.

Abstract: A mapping circuit includes a linear circuit for outputting a signal which is linearly changed with respect to its input, a non-linear circuit for outputting a signal which is non-linearly changed with respect to its input, and an adder for summing the output signals of the linear and non-linear circuits and an external input signal. A chaotic neuron circuit using the mapping circuit has a simple structure and more precise chaos characteristics. A chaotic neural network can thus be formed by the serial and/or parallel interconnection of a plurality of chaotic neuron circuits, wherein the weight of each neuron is controlled.

Abstract: A semiconductor package including a semiconductor chip having at its upper surface a plurality of bonding pads and a tape lead frame having a paddle on which a semiconductor chip is laid, a plurality of inner leads each having a sufficient length to be directly connected with each corresponding bonding pad of the semiconductor chip and a plurality of outer leads each connected with each corresponding inner lead and having a thickness larger than that of the inner lead. The semiconductor chip is die bonded on the paddle of the tape lead frame. An insulating layer is formed over the upper surface of the semiconductor chip except for portions corresponding the bonding pads. Each inner lead has at its one end a bonding bumper for electrically connecting the inner lead with each corresponding bonding pad. Using the epoxy molding compound, the inner leads and the paddle of the tape lead frame, the semiconductor and the insulating layer are molded.

Abstract: A chaotic recurrent neural network includes N chaotic neural networks for receiving an external input and the outputs of N-1 chaotic neural networks among said N chaotic neural networks and performing an operation according to the following dynamic equation ##EQU1## wherein W.sub.ij is a synapse connection coefficient of the feedback input from the "j"th neuron to the "i"th neuron, X.sub.i (t) is the output of the "i"th neuron at time t, and .gamma..sub.i, .alpha. and and k are a time-delaying constant, a non-negative parameter and a refractory time attenuation constant, respectively, and wherein Z.sub.i (t) represents X.sub.i (t) when i belongs to the neuron group I and represents a.sub.i (t) when i belongs to the external input group E. Also, a learning algorithm for the chaotic recurrent neural network increases its learning efficiency.

Abstract: The present invention relates to a method for fabrication of a mask capable of stabilizing the size and the thickness thereof.A method for fabrication of a mask according to the present invention comprises a step for successively depositing an oxide layer and a Cr layer on a quartz plate, a step for successively etching said oxide layer and said Cr layer by an E-beam, and a step for extending said oxide in volume by an oxidation process to form a phase-shifter.Therefore, the size and thickness of a mask can easily be controlled by using an oxide instead of PMMA of the photosensitive film as a phase-shifter and endurability of a mask can be improved.

Abstract: A non-linear circuit includes a first variable resistor one end of which is applied with an input signal, an amplifier whose inverting input is connected to the other end of the first variable resistor and whose non-inverting input is connected to ground, a second variable resistor one end of which is connected to the inverting input of the amplifier, a third variable resistor one end of which is connected to the output of the amplifier and the other end being connected to the other end of the second variable resistor, and a fourth variable resistor one end of which is applied with the input signal and the other end being connected to the third variable resistor.

Abstract: A control circuit for refreshing a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns. The inventive refresh control circuit includes a first circuit for detecting whether a first refresh mode exists in response to row and column address signals applied thereto and for generating a first output signal based on the result of the detection; a second circuit for detecting whether a second refresh mode exists in response to row and column address signals applied thereto and for generating a second output signal based on the result of the detection; a third circuit for detecting whether a reset condition exists in response to row and column address signals applied thereto and for generating a reset signal based on the result of the detection; and a counter circuit, coupled to the first, second, and third detecting circuits, for generating a count value representing a refresh address in response to the first and second output signals and the reset signal.

Abstract: A speech recognition system for recognizing the remote-controlling vocal commands of TV sets and VCRs comprises a microphone for receiving the speech pronounced by a user; a speech analyzer for analyzing the speech input via the microphone; circuitry for detecting a vocal section of the speech from the speech analyzer and performing a time-axis normalization and a binarization for the detected vocal section; and a multilayer neural network for receiving the binarization data from the aforementioned circuitry and then performing the learning, to thereby output the speech recognition result. Accordingly, the present invention can enhance the recognition ratio of speech.

Abstract: A self-learning multi layer neural network and the learning method thereof are characterized in that N-bit input data and M-bit desired output data are received, a weight value of each synapse is adjusted so as to produce output data corresponding to the input data, and self-learning is performed while proceeding to a next layer. Thus, it is not necessary for the user to input and adjust all the weight values of the respective synapse while the network performs self-learning and a desired function.

Abstract: A programmable multilayer neural network includes a weight storing circuit for storing the weight of each synapse to perform an intended function, an interfacing circuit for transmitting the weight value stored in the storing circuit to each synapse, and a multilayer neural network circuit programmed to have the weight from the weight storing circuit and for outputting an intended output.

Abstract: A synapse MOS transistor has gate electrodes of different lengths, different widths or different lengths and widths, between one source region and one drain region. Thus, when using the synapse MOS transistor to implement a neural network, the chip area can be greatly reduced.

Abstract: A tester applicable to semiconduction chips having a plurality of pins. The tester comprises a TAB tape having an adhesive surface and a plurality of connecting wires attached to the adhesive surface of the TAB tape and connected to a test card. At a probe region of the tester, probe tips are disposed which come into contact with pads of the semiconductor chip to be tested, upon testing. Each probe tip is made of a palladium layer having a serrated edge grown to shape over a nickel film on a portion of each connecting wire, which portion is disposed at the probe region. The tester can test a semiconductor chip having a plurality of pins and carry out simultaneous probings of a semiconductor chip having the number of pins enabling a TAB chip bonding. Both a functional test and a burn-in test may be carried out with a single test system. Since the tester has many sharp probe tips made of dendritic-grown palladium, it can provide an improvement in proving effect.

Abstract: The present invention relates to a semiconductor and a method for fabrication thereof and particularly to a semiconductor having a field oxide having a shape such that the lower part is wider that the upper part.Therefore, according to the present invention, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased. Furthermore, because LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because a field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled.

Abstract: A method for making a hole capacitor for DRAM cell includes the steps of: depositing a nitride layer and a lower oxide layer, and forming a buried contact hole, after forming a MOS transistor upon a semiconductor substrate. Thereafter depositing an in-situ doped non-crystalline silicon layer, an undoped non-crystalline silicon layer, and a hemispherical polysilicon layer in all in sequence with a thickness of 1500 .ANG. or over. An upper oxide film is deposited, and then, carrying out an etch-back on the upper oxide film so that the hemispherical polysilicon domes are exposed. Etching the polysilicon layers using the remained portions of the upper oxide film remaining on the valleys of the hemispherical polysilicon as a mask, in order to form a plurality of holes perforated from the domes to the insulating layer located under the layers. The upper oxide film is removed through an etch process.

Abstract: This invention relates to a method for fabricating a semiconductor memory device with a large capacitance, which comprises the steps of forming a gate insulating film, a gate electrode and a source and drain region on a semiconductor substrate, forming an interlayer and an etch stopper on the whole surface, etching selectively away the etch stopper and the interlayer to form an opening, forming a first conductive layer, a first insulating film and a second insulating film on the whole surface, etching selectively away the first and second insulating film, forming a side wall spacer of a third insulating film on the side of the first and second insulating film, forming a fourth insulating film on the whole surface, etching selectively away the fourth insulating film, removing the second insulating film and the side wall spacer, forming a second conductive layer on the whole surface, etching selectively away the second conductive layer and the first insulating film and the first conductive layer, removing the f

Abstract: A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved.

Abstract: A method for fabricating a mask ROM capable of reducing the processing time taken in fabricating the MROM by the manufacturer after the order by the user, thus improving the productivity. For fabricating the mask ROM, first, a fabrication of a MOS transistor is achieved by forming a gate oxide film, a gate electrode and source/drain regions on a semiconductor substrate. After the formation of the MOS transistor, a BPSG film, a metal electrode, a passivation film and a pad are sequentially formed. Finally the implantation of ROM code ions in accordance with the user's order is carried out, completing the fabrication of the MROM. It is possible to reduce the processing time (turn around time) taken in fabricating the MROM by the manufacturer after the order by the user because the ROM code ion implantation is carried out at the final stage of the MROM fabrication.

Abstract: A CCD image sensor comprising: a semiconductor substrate of a first conductivity type connected to a ground; an impurity region of a second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type, to serve as a blooming prevention layer; an impurity region of the first conductivity type formed in the surface of the semiconductor substrate, so that it encloses the impurity region of the second conductivity type serving as a blooming prevention layer, to serve as a potential barrier layer; an impurity region of the second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type so that it encloses the impurity region of the first conductivity type serving as a potential barrier layer, to serve as a light receiving region; an insulation film which is formed on the surface of the semiconductor substrate of the first conductivity type and has contact holes at both edges of the impurity region of the second conductivity type,

Abstract: The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

Abstract: A CCD package and a method for assembling a CCD package utilizing a TAB process. The method comprises the steps of preparing a tape for TAB which has outer leads, inner leads and die bonding paddles, bonding a chip on the paddles and then bonding the free ends of the inner leads on the bonding pads of the chip, connecting the inner leads and the outer leads through insulations, adding a light shield layer beneath the chip, and attaching a glass lid to the surface portions of the inner leads positioned just above the chip. Accordingly, packages of light, laminated and simple structure can be obtained, thereby advantageously enabling the compactness of products utilizing CCD elements. Also, the process is also simplified, thereby decreasing the cost of producing CCD elements.