Abstract: A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may b e coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.

Abstract: A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.

Abstract: Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.

Abstract: An impactor is externally securable to a container of flowable material to break up bridging or clumping of the material in the container. The impactor comprises a strike plate mountable to an outlet hopper or the like and a drive which axially reciprocally moves the hammer, such that operation of the drive causes the hammer to impact the strike plate to thereby pass vibrations into the container.

Abstract: A plank (10) used to construct a platform such as a catwalk (C3, C4) extending about the exterior or interior of a building (B) includes first and second generally horizontal sections (12, 22). The second generally horizontal section of the plank extends from one side of the first section. During construction of the platform, the first section of one plank overlaps the second section of an adjacent plank. A third generally vertical section (52) of the plank extends generally perpendicularly from one side of the second section and includes lips (58, 60) at its inner and outer ends for attaching the plank to toe boards (40, 44) to secure the plank to the frames. When installed, the planks extend from a side of the building. The resulting catwalk extends either in a straight line, or is curved, depending upon the amount of overlap the first and second sections of the respective planks.

Abstract: Systems and methods of data inversion, circuitry, detection and/or schemes are disclosed. According to illustrative implementations, exemplary circuitry may include static detection or detection circuitry such as those involving static current sources to detect a threshold for data inversion, pre-conditioning of detection circuitry, and/or active detection circuitry or schemes. In some implementations, exemplary memory or data inversion circuitry may comprise a transistor array, a bias generator, and a sense amplifier, wherein the transistor array may comprise at least one pair of transistor circuits arranged so that an output of the transistor array is provided as a sum or function of signal/current outputs of at least some of the transistor circuits in the array. As set forth, various systems, methods and circuitry herein may posses only a 3 static gate delay, such that very high speed and/or fast flow-through is achieved.

Abstract: The present disclosure relates to a method and to an irradiation system for irradiating a moving target volume with an ion beam, in particular for tumor therapy, wherein ion radiography measurements of the target volume are performed and the irradiation for deposition purposes and for radiography purposes is performed with the same ion beam but consecutively in time by alternating the energy of the ion beam between a higher radiography energy and a lower deposition energy using, for example, a passive energy modulator proximal with respect to the patient.

Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.

Abstract: A commuter java press provides a thermally insulated first cylindrical vessel having and open top and a closed bottom and a second cylindrical vessel axially carried in fluid tight engagement within a volume defined by the first cylindrical vessel, the second cylindrical vessel having an open top and a fluid permeable filter at a bottom portion. A cap threadably engages with the top portion of the second cylindrical vessel and a flip top is user operable to optionally close and open a drinking orifice defined in the cap.

Abstract: Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from control circuitry.

Abstract: A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. The computing device additionally includes at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from the first section and a decoder to activate a word line connected to a cell in the column in the second section to write the bit line voltage into the cell.

Abstract: Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.

Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Abstract: A search unit including a distributor TCAM and a DRAM search unit and a method to divide a database of TCAM rules is disclosed. The method includes selecting a rule having multiple “don't care” values and selecting a bit of the rule having a “don't care” value, generating two distributor rules based on the selected rule, associating rules of the database which match each of the distributor rules with the distributor rule they match to create subset databases, and repeating the steps of selecting, generating and associating until the average number of rules in each subset database is at or below a predefined amount. A DRAM storage unit has a section for each subset database, where each section is pointed to by a different distributor rule. A DRAM search unit matches an input key to one of the rules in the section pointed to by the matched distributor rule.

Abstract: An energy filter device for radiation includes at least one focusing device configured as an energy-dependent focusing device and at least one beam separating device.

Abstract: Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.