Abstract: Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

Abstract: In one embodiment, a system, comprising: a damper assembly, the damper assembly comprising: a structural member; at least one door pivotably coupled to the structural member; a clip connected to the damper assembly and comprising plural spring end constraining segments; a spring comprising a first end and a second end, wherein at least the first end comprises a hook, the spring coupled at the first end to one of the plural spring end constraining segments and at the second end fixably coupled to the damper assembly, the clip configured to accept a hookable connection to the spring at any one of the plural spring end constraining segments, each of the plural spring end constraining segments constraining movement of the hook, when connected thereto, during opening and closing of the at least one door, wherein the spring is at a first tension when hooked to the one of the plural spring end constraining segments and at a second tension when hooked to another of the plural spring end constraining segments.

Abstract: A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored in a different column of the array and each add operation occurs in its associated different column.

Abstract: In one embodiment, a method executed by a computing system, comprising: receiving pixel samples from three-dimensional (3D) data corresponding to one or more images comprising one or more animals; fitting curves for the received pixel samples; deriving parameters from the curves; determining measurements based on variations in the parameters; and estimating a weight of the one or more animals by applying one or more regression algorithms to the measurements.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder. The storage section stores a first copy, a second copy and a third copy of a data item in physically separated columns. The comparison section temporarily stores the first copy in a first row and the second copy in a second row. The comparing element compares between bits of the first and second rows and provides at least one per bit change indication. The selective write unit receives at least one per bit change indication and fetches from the third copy a correct value for each bit having a positive bit change indication. The row decoder concurrently writes each correct value back to its bit location in the first and second copies.

Abstract: An associative processor includes a memory array and a controller. The memory array stores a multiplicity of N bit stochastic numbers in separate rows of a stochastic section of the memory array and each stochastic number has a same probability distribution P. The controller includes a probability calculator which receives a desired probability distribution Pdesired, determines a Boolean function of a set of the N bit stochastic numbers which produces the probability distribution Pdesired and activates associated rows of the stochastic numbers to implement the function on the rows to produce a resultant stochastic number having the probability distribution Pdesired.

Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Abstract: A climate control system (20) for an animal house (10) is configured by determining a minimum ventilation curve for required minimum ventilation. A plurality of ventilation stages is created based on the minimum ventilation curve and the plurality of ventilation fans (23) in the climate control system, each stage providing a percentage of the required minimum ventilation. Creating the stages includes prioritizing the ventilation fans to create a selection hierarchy and determining a minimum stage ventilation and a maximum stage ventilation for each stage. Ventilation fans are selected following the hierarchy that provides the desired percentage of the minimum required ventilation. An increment between a maximum stage ventilation and a minimum stage ventilation for the next higher stage is defined, wherein the minimum capacity level is a function of the minimum capacity of the group of fans added to the next higher stage and the maximum capacity for the next higher stage is determined based on the increment.

Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Abstract: Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).

Abstract: An axially collapsible cooking vessel comprises a flexible body having plural circumferentially extending reduced thickness areas spacedly arrayed between an upper peripheral edge and a bottom edge that provide for nested folding of the flexible body axially inwardly and downwardly upon itself; a heat conductive base that is interconnected with a bottom peripheral edge of the flexible body in a fluid tight engagement therewith; a heatsink structurally interconnected to a bottom surface of the heat conductive base, the heatsink having an annular shaped radiator and a circumferentially extending shield extending about the annular shaped radiator; and a removable lid releasable engageable with a top opening defined by the flexible body.

Abstract: An agricultural dryer assembly has a fan apparatus and burner assembly that form a longitudinal dryer axis. An airflow transition mechanism is positioned between the fan apparatus and the burner assembly and has an endcap with an end plate that is substantially perpendicular to the dryer axis. A transition housing has an upstream end proximate the fan apparatus having a first diameter and a downstream end proximate the burner assembly having a second size, and an open middle. The airflow transition mechanism also includes an end plate perpendicular to the airflow and for a single burner configuration, a first and second air-directing crossing members and for a dual burner configuration, two inlet devices positioned in a middle opening of the transition housing that extend through the axis of the fan heater assembly.

Abstract: A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry. In some embodiments, the system and circuit may involve or be configured for coupling with lock loop circuitry such as phase locked loop (PLL) circuitry and/or a delay locked loop (DLL) circuitry. For example, one illustrative implementation may include or involve a phase locked loop (PLL) with distributed duty cycle correction loop/circuitry.

Abstract: The present invention relates to the use of a porous polymer etched ion-track membrane as separator for batteries comprising a positive electrode, a negative electrode and a liquid electrolyte comprising at least one salt of a cationic ion in solution in a solvent, and to batteries comprising such a membrane as porous separator.

Abstract: A method for an associative memory device includes replacing a set of three multi-bit binary numbers P, Q and R, stored in the associative memory device, with two multi-bit binary numbers X and Y, also stored in the associative memory device, wherein a sum of the binary numbers P, Q and R is equal to a sum of the binary numbers X and Y. A system includes an associative memory array having rows and columns and a multi-bit multiplier. Each column of the array stores two multi-bit binary numbers to be multiplied. The multi-bit multiplier multiplies, in parallel, the two multi-bit binary numbers per column by concurrently processing all bits of partial products generated by the multiplier. The multiplier performs the processing without any carry propagation delay when adding all but the last two partial products.

Abstract: A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: An animal feeder has a hopper for receiving feed, the hopper having converging front panels with lower ends defining an elongate chute through which feed is directed. A shield is attached to each of the front panels and diverges from the front panel forming a cove that remains free of feed. A trough extends along the feeder and a water supply duct delivers water into the trough. An elongate shelf has a feed platform for receiving feed from the hopper. The shelf is positioned above the trough such that any feed falling, falls into the trough. The shelf has shelf retainers running longitudinally of the shelf above the feed platform, each shelf retainer directed between its respective shield and front panel. A height-adjusting mechanism adjusts the vertical position of the shelf relative the hopper and the trough. As the shelf moves upward, the shelf retainer moves into the cove.

Abstract: A method to add a first one bit variable with a second one bit variable and a carry-in bit, to generate a sum bit and a carry-out bit, the method includes initiating the sum bit to the value of the second one bit variable, initiating the carry-out bit to a value of the carry-in bit and modifying the sum bit and the carry-out bit if a comparison of a sequence of the first one bit variable, the second one bit variable and an inverse value of the carry-in bit matches one of a predefined set of a change trigger sequences.

Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.